[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Feb 20 10:27:09 PST 2022

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craig.topper added a comment.

Ping. Anyone have other comments?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119171/new/

https://reviews.llvm.org/D119171

Previous message: [PATCH] D118595: [AARCH64][DAGCombine] Add combine for negation of CSEL absolute value pattern.
Next message: [PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).
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