[PATCH] D120094: [CallingConv] Generate isArgumentRegister() predicate via tablegen

[Bill Wendling via Phabricator via llvm-commits]

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This predicate piggybacks off of the *CallingConv.td information. (The
generated code is similarly structured to the code that allocates an
argument register.) Because of this, some of the generated code results
in a no-op. Unfortuantely, but not harmful.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120094

Files:
  llvm/include/llvm/CodeGen/CallingConvLower.h
  llvm/include/llvm/CodeGen/MachineRegisterInfo.h
  llvm/include/llvm/CodeGen/TargetRegisterInfo.h
  llvm/lib/CodeGen/MachineRegisterInfo.cpp
  llvm/lib/CodeGen/PrologEpilogInserter.cpp
  llvm/lib/Target/AArch64/AArch64CallingConvention.cpp
  llvm/lib/Target/AArch64/AArch64CallingConvention.h
  llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
  llvm/lib/Target/AArch64/AArch64RegisterInfo.h
  llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
  llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
  llvm/lib/Target/AMDGPU/R600RegisterInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
  llvm/lib/Target/ARM/ARMCallingConv.cpp
  llvm/lib/Target/ARM/ARMCallingConv.h
  llvm/lib/Target/AVR/AVRCallingConv.h
  llvm/lib/Target/AVR/AVRISelLowering.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.cpp
  llvm/lib/Target/AVR/AVRRegisterInfo.h
  llvm/lib/Target/BPF/BPFISelLowering.cpp
  llvm/lib/Target/BPF/BPFRegisterInfo.cpp
  llvm/lib/Target/BPF/BPFRegisterInfo.h
  llvm/lib/Target/Hexagon/HexagonCallingConv.h
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
  llvm/lib/Target/Hexagon/HexagonRegisterInfo.h
  llvm/lib/Target/Lanai/LanaiISelLowering.cpp
  llvm/lib/Target/Lanai/LanaiRegisterInfo.cpp
  llvm/lib/Target/Lanai/LanaiRegisterInfo.h
  llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
  llvm/lib/Target/MSP430/MSP430RegisterInfo.h
  llvm/lib/Target/Mips/MipsFastISel.cpp
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.cpp
  llvm/lib/Target/Mips/MipsRegisterInfo.h
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCCallingConv.cpp
  llvm/lib/Target/PowerPC/PPCCallingConv.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/Sparc/SparcISelLowering.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
  llvm/lib/Target/Sparc/SparcRegisterInfo.h
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
  llvm/lib/Target/SystemZ/SystemZRegisterInfo.h
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/VE/VERegisterInfo.cpp
  llvm/lib/Target/VE/VERegisterInfo.h
  llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.h
  llvm/lib/Target/X86/X86CallingConv.cpp
  llvm/lib/Target/X86/X86CallingConv.h
  llvm/lib/Target/X86/X86RegisterInfo.cpp
  llvm/lib/Target/X86/X86RegisterInfo.h
  llvm/lib/Target/XCore/XCoreISelLowering.cpp
  llvm/lib/Target/XCore/XCoreRegisterInfo.cpp
  llvm/lib/Target/XCore/XCoreRegisterInfo.h
  llvm/utils/TableGen/CallingConvEmitter.cpp

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