[PATCH] D119532: [RISCV] Extend sext.w removal pass to remove unused sign-extensions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:116
+    case RISCV::SLLI:
+      if (MI->getOperand(2).getImm() >= 32)
+        continue;
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The register form is handled without knowing anything about the shift amount operand. So why does the immediate value matter?


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:120
+      continue;
+    case RISCV::ANDI:
+      if (isUInt<11>(MI->getOperand(2).getImm()))
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Similar question.


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Comment at: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp:298
+    case RISCV::BSETI:
+      if (MI->getOperand(2).getImm() >= 32)
+        return false;
----------------
Can't changing bit 31 break the sign extension?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119532/new/

https://reviews.llvm.org/D119532