[llvm] ea0676f - [SystemZ][z/OS] Fix f32 variadic argument assertion
Voss, Matthew via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 15 19:58:53 PST 2022
Hi Neumann,
The tests in this commit fail on this linux build bot and our internal CI with the following error. Could you take a look?
Buildbot: https://lab.llvm.org/buildbot/#/builders/58/builds/18483
Command Output (stderr):
--
/data/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll:203:15: error: CHECK-NEXT: is not on the line after the previous match
; CHECK-NEXT: stg 0, 2200(4)
^
<stdin>:526:2: note: 'next' match was here
stg 0, 2200(4)
^
<stdin>:523:21: note: previous match ended here
llihf 0, 1073692672
^
<stdin>:524:1: note: non-matching line after previous match is here
llihh 2, 16384
^
Input file: <stdin>
Check file: /data/u1/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
-dump-input=help explains the following input dump.
Input was:
<<<<<<
.
.
.
521: larl 1, @CPI17_0
522: le 0, 0(1)
523: llihf 0, 1073692672
524: llihh 2, 16384
525: llihh 3, 16392
526: stg 0, 2200(4)
next:203 !~~~~~~~~~~~~~ error: match on wrong line
527: brasl 7, pass_vararg4 at PLT
528: bcr 0, 3
529: lg 7, 2072(4)
530: aghi 4, 192
531: b 2(7)
532: * -- End function
>>>>>>
--
********************
********************
Failed Tests (1):
LLVM :: CodeGen/SystemZ/call-zos-vararg.ll
Thanks,
Matt
> -----Original Message-----
> From: llvm-commits <llvm-commits-bounces at lists.llvm.org> On Behalf Of
> Neumann Hon via llvm-commits
> Sent: Tuesday, February 15, 2022 3:13 PM
> To: llvm-commits at lists.llvm.org
> Subject: [llvm] ea0676f - [SystemZ][z/OS] Fix f32 variadic argument
> assertion
>
>
> Author: Mubariz Afzal
> Date: 2022-02-15T18:11:57-05:00
> New Revision: ea0676f97d734196b15da7553cd407e6a36cef2d
>
> URL: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> project/commit/ea0676f97d734196b15da7553cd407e6a36cef2d__;!!JmoZiZGBv3RvKR
> Sx!pzaE29jtfXHs9rzfvJCFh1cq8rvpB8-auoSheaJdsvCLBM4QT4AP_guFJl7Jy_Fg9g$
> DIFF: https://urldefense.com/v3/__https://github.com/llvm/llvm-
> project/commit/ea0676f97d734196b15da7553cd407e6a36cef2d.diff__;!!JmoZiZGBv
> 3RvKRSx!pzaE29jtfXHs9rzfvJCFh1cq8rvpB8-
> auoSheaJdsvCLBM4QT4AP_guFJl56r8q0vQ$
>
> LOG: [SystemZ][z/OS] Fix f32 variadic argument assertion
>
> The tablegen lines that specify the XPLINK64 calling convention for
> promoting an f32 vararg to an f64 are effectively overwritten by the
> following tablegen line which bitcast an f64 vararg to an i64 (so that it
> can be used in the GPRs). It becomes a bitcast from f32 to i64.
>
> Since we don't handle a bitcast for f32s this caused an assertion.
>
> Added:
>
>
> Modified:
> llvm/lib/Target/SystemZ/SystemZCallingConv.td
> llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
> llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
>
> Removed:
>
>
>
> ##########################################################################
> ######
> diff --git a/llvm/lib/Target/SystemZ/SystemZCallingConv.td
> b/llvm/lib/Target/SystemZ/SystemZCallingConv.td
> index a7ea5e1e4bf8..bc5f6a15d493 100644
> --- a/llvm/lib/Target/SystemZ/SystemZCallingConv.td
> +++ b/llvm/lib/Target/SystemZ/SystemZCallingConv.td
> @@ -225,9 +225,10 @@ def CC_SystemZ_XPLINK64 : CallingConv<[
> // XPLINK64 ABI compliant code widens integral types smaller than i64
> // to i64 before placing the parameters either on the stack or in
> registers.
> CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
> - // Promote f32 to f64 and bitcast to i64, if it needs to be passed in
> GPRS.
> - CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
> - CCIfType<[f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
> + // Promote f32 to f64 and bitcast to i64, if it needs to be passed in
> GPRs.
> + // Although we assign the f32 vararg to be bitcast, it will first be
> + promoted // to an f64 within convertValVTToLocVT().
> + CCIfType<[f32, f64], CCIfNotFixed<CCBitConvertToType<i64>>>,
> // long double, can only be passed in GPR2 and GPR3, if available,
> // hence R2Q
> CCIfType<[f128],
> CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
>
> diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
> b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
> index 0eded62347be..c125ceed3fcb 100644
> --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
> +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
> @@ -1358,8 +1358,12 @@ static SDValue convertValVTToLocVT(SelectionDAG
> &DAG, const SDLoc &DL,
> return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
> case CCValAssign::BCvt: {
> assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128);
> - assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f64 ||
> - VA.getValVT() == MVT::f128);
> + assert(VA.getValVT().isVector() || VA.getValVT() == MVT::f32 ||
> + VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::f128);
> + // For an f32 vararg we need to first promote it to an f64 and then
> + // bitcast it to an i64.
> + if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64)
> + Value = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f64, Value);
> MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() ==
> MVT::i64
> ? MVT::v2i64
> : VA.getLocVT();
>
> diff --git a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
> b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
> index 2efe27172efc..8e4974c36cad 100644
> --- a/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
> +++ b/llvm/test/CodeGen/SystemZ/call-zos-vararg.ll
> @@ -189,7 +189,30 @@ entry:
> ret i64 %retval
> }
>
> +; CHECK-LABEL: call_vararg_float0
> +; CHECK: lghi 1, 1
> +; CHECK: llihf 2, 1073692672
> +define i64 @call_vararg_float0() {
> +entry:
> + %retval = call i64 (i64, ...) @pass_vararg2(i64 1, float 1.953125)
> + ret i64 %retval
> +}
> +
> +; CHECK-LABEL: call_vararg_float1
> +; CHECK: llihf 0, 1073692672
> +; CHECK-NEXT: stg 0, 2200(4)
> +; CHECK: larl 1, @CPI21_0
> +; CHECK-NEXT: le 0, 0(1)
> +; CHECK: llihh 2, 16384
> +; CHECK: llihh 3, 16392
> +define i64 @call_vararg_float1() {
> +entry:
> + %retval = call i64 (float, ...) @pass_vararg4(float 1.0, float 2.0,
> +float 3.0, float 1.953125)
> + ret i64 %retval
> +}
> +
> declare i64 @pass_vararg0(i64 %arg0, i64 %arg1, ...) declare i64
> @pass_vararg1(fp128 %arg0, ...) declare i64 @pass_vararg2(i64 %arg0, ...)
> declare i64 @pass_vararg3(...)
> +declare i64 @pass_vararg4(float, ...)
>
>
>
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