[PATCH] D119552: [TableGen][AMDGPU] Allow empty register classes

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/utils/TableGen/RegisterInfoEmitter.cpp:1051-1065
+      OS << "  // " << Name << " Register Class...\n"
+         << "  const MCPhysReg " << Name << "[] = {\n    ";
+      for (Record *Reg : Order) {
+        OS << getQualifiedName(Reg) << ", ";
+      }
+      OS << "\n  };\n\n";
 
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nhaehnle wrote:
> Whitespace looks off. Is this using tabs?
It looks OK to me. There are no tabs.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119552/new/

https://reviews.llvm.org/D119552