[PATCH] D119552: [TableGen][AMDGPU] Allow empty register classes

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle added a comment.

Nice cleanup :)



================
Comment at: llvm/utils/TableGen/RegisterInfoEmitter.cpp:1051-1065
+      OS << "  // " << Name << " Register Class...\n"
+         << "  const MCPhysReg " << Name << "[] = {\n    ";
+      for (Record *Reg : Order) {
+        OS << getQualifiedName(Reg) << ", ";
+      }
+      OS << "\n  };\n\n";
 
----------------
Whitespace looks off. Is this using tabs?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119552/new/

https://reviews.llvm.org/D119552