[llvm] cb199e0 - [MC] Define and use MCRegisterInfo::regsOverlap
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Mon Feb 14 12:48:24 PST 2022
Author: Jay Foad
Date: 2022-02-14T20:46:02Z
New Revision: cb199e0fca32e493d30112cc21417ff0e1e04ba9
URL: https://github.com/llvm/llvm-project/commit/cb199e0fca32e493d30112cc21417ff0e1e04ba9
DIFF: https://github.com/llvm/llvm-project/commit/cb199e0fca32e493d30112cc21417ff0e1e04ba9.diff
LOG: [MC] Define and use MCRegisterInfo::regsOverlap
Separate MCRegisterInfo::regsOverlap out from
TargetRegisterInfo::regsOverlap. This is useful in the AMDGPU AsmParser
where we only have access to MCRegisterInfo.
Differential Revision: https://reviews.llvm.org/D119533
Added:
Modified:
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/MC/MCRegisterInfo.h
llvm/lib/MC/MCRegisterInfo.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
index 7b8d270c3cc2..d8aeb31a1731 100644
--- a/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetRegisterInfo.h
@@ -415,19 +415,11 @@ class TargetRegisterInfo : public MCRegisterInfo {
/// Returns true if the two registers are equal or alias each other.
/// The registers may be virtual registers.
- bool regsOverlap(Register regA, Register regB) const {
- if (regA == regB) return true;
- if (!regA.isPhysical() || !regB.isPhysical())
- return false;
-
- // Regunits are numerically ordered. Find a common unit.
- MCRegUnitIterator RUA(regA.asMCReg(), this);
- MCRegUnitIterator RUB(regB.asMCReg(), this);
- do {
- if (*RUA == *RUB) return true;
- if (*RUA < *RUB) ++RUA;
- else ++RUB;
- } while (RUA.isValid() && RUB.isValid());
+ bool regsOverlap(Register RegA, Register RegB) const {
+ if (RegA == RegB)
+ return true;
+ if (RegA.isPhysical() && RegB.isPhysical())
+ return MCRegisterInfo::regsOverlap(RegA.asMCReg(), RegB.asMCReg());
return false;
}
diff --git a/llvm/include/llvm/MC/MCRegisterInfo.h b/llvm/include/llvm/MC/MCRegisterInfo.h
index 65436dc74c3e..7165a2982d1b 100644
--- a/llvm/include/llvm/MC/MCRegisterInfo.h
+++ b/llvm/include/llvm/MC/MCRegisterInfo.h
@@ -580,6 +580,9 @@ class MCRegisterInfo {
bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const {
return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
}
+
+ /// Returns true if the two registers are equal or alias each other.
+ bool regsOverlap(MCRegister RegA, MCRegister RegB) const;
};
//===----------------------------------------------------------------------===//
@@ -698,6 +701,11 @@ class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
// unit, we can allow a 0
diff erential here.
advance();
}
+
+ MCRegUnitIterator &operator++() {
+ MCRegisterInfo::DiffListIterator::operator++();
+ return *this;
+ }
};
/// MCRegUnitMaskIterator enumerates a list of register units and their
diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp
index d491c0eb7e06..d6c4fe10fc98 100644
--- a/llvm/lib/MC/MCRegisterInfo.cpp
+++ b/llvm/lib/MC/MCRegisterInfo.cpp
@@ -122,3 +122,14 @@ int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const {
: Twine(RegNum)));
return I->second;
}
+
+bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
+ // Regunits are numerically ordered. Find a common unit.
+ MCRegUnitIterator RUA(RegA, this);
+ MCRegUnitIterator RUB(RegB, this);
+ do {
+ if (*RUA == *RUB)
+ return true;
+ } while (*RUA < *RUB ? (++RUA).isValid() : (++RUB).isValid());
+ return false;
+}
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 0143ae859035..7ff4988c3dd3 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -3371,7 +3371,6 @@ AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
assert(DstIdx != -1);
const MCOperand &Dst = Inst.getOperand(DstIdx);
assert(Dst.isReg());
- const unsigned DstReg = mc2PseudoReg(Dst.getReg());
const int SrcIndices[] = { Src0Idx, Src1Idx, Src2Idx };
@@ -3379,8 +3378,8 @@ AMDGPUAsmParser::validateEarlyClobberLimitations(const MCInst &Inst,
if (SrcIdx == -1) break;
const MCOperand &Src = Inst.getOperand(SrcIdx);
if (Src.isReg()) {
- const unsigned SrcReg = mc2PseudoReg(Src.getReg());
- if (isRegIntersect(DstReg, SrcReg, TRI)) {
+ if (TRI->regsOverlap(Dst.getReg(), Src.getReg())) {
+ const unsigned SrcReg = mc2PseudoReg(Src.getReg());
Error(getRegLoc(SrcReg, Operands),
"destination must be
diff erent than all sources");
return false;
@@ -3643,7 +3642,7 @@ bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
if (TRI->getRegClass(Desc.OpInfo[0].RegClass).getSizeInBits() <= 128)
return true;
- if (isRegIntersect(Src2Reg, DstReg, TRI)) {
+ if (TRI->regsOverlap(Src2Reg, DstReg)) {
Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),
"source 2 operand must not partially overlap with dst");
return false;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 7c4780c5062a..23f8bad9ab6e 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1528,13 +1528,6 @@ bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
Reg == AMDGPU::SCC;
}
-bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI) {
- for (MCRegAliasIterator R(Reg0, TRI, true); R.isValid(); ++R) {
- if (*R == Reg1) return true;
- }
- return false;
-}
-
#define MAP_REG2REG \
using namespace AMDGPU; \
switch(Reg) { \
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index fc8e26313d0e..d24a420cf707 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -779,9 +779,6 @@ bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI);
/// Is Reg - scalar register
bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
-/// Is there any intersection between registers
-bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
-
/// If \p Reg is a pseudo reg, return the correct hardware register given
/// \p STI otherwise return \p Reg.
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
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