[PATCH] D119171: [SelectionDAG][RISCV][ARM][PowerPC][X86][WebAssembly] Change default abs expansion to use sra (X, size(X)-1); sub (xor (X, Y), Y).

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

I've no objections to using this instead of D119099 <https://reviews.llvm.org/D119099>, even with the x86 i8 codegen change



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Comment at: llvm/test/CodeGen/RISCV/rv64zbb.ll:959
 
 ; FIXME: We can remove the sext.w by using addw for RV64I and negw for RV64ZBB.
 define signext i32 @abs_i32_sext(i32 signext %x) {
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update FIXME?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119171/new/

https://reviews.llvm.org/D119171