[llvm] 2aa732a - [X86][MS] Fix the wrong alignment of vector variable arguments on Win32
Phoebe Wang via llvm-commits
llvm-commits at lists.llvm.org
Sat Feb 12 18:23:27 PST 2022
Author: Phoebe Wang
Date: 2022-02-13T10:23:18+08:00
New Revision: 2aa732a9183b8fa23c103c169a5da0e90cc67cf5
URL: https://github.com/llvm/llvm-project/commit/2aa732a9183b8fa23c103c169a5da0e90cc67cf5
DIFF: https://github.com/llvm/llvm-project/commit/2aa732a9183b8fa23c103c169a5da0e90cc67cf5.diff
LOG: [X86][MS] Fix the wrong alignment of vector variable arguments on Win32
D108887 fixed alignment mismatch by changing the caller's alignment in
ABI. However, we found some cases that still assume the alignment is
vector size. This patch fixes them to avoid the runtime crash.
Reviewed By: rnk
Differential Revision: https://reviews.llvm.org/D114536
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/test/CodeGen/X86/vaargs-win32.ll
llvm/test/CodeGen/X86/win32-spill-xmm.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index b98ac635e00dd..446be6751f110 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3569,10 +3569,15 @@ X86TargetLowering::LowerMemArgument(SDValue Chain, CallingConv::ID CallConv,
MFI.setObjectSExt(FI, true);
}
+ MaybeAlign Alignment;
+ if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
+ ValVT != MVT::f80)
+ Alignment = MaybeAlign(4);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getLoad(
ValVT, dl, Chain, FIN,
- MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI));
+ MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
+ Alignment);
return ExtendedInMem
? (VA.getValVT().isVector()
? DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VA.getValVT(), Val)
@@ -4091,9 +4096,14 @@ SDValue X86TargetLowering::LowerMemOpCallTo(SDValue Chain, SDValue StackPtr,
if (isByVal)
return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
+ MaybeAlign Alignment;
+ if (Subtarget.isTargetWindowsMSVC() && !Subtarget.is64Bit() &&
+ Arg.getSimpleValueType() != MVT::f80)
+ Alignment = MaybeAlign(4);
return DAG.getStore(
Chain, dl, Arg, PtrOff,
- MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset));
+ MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
+ Alignment);
}
/// Emit a load of return address if tail call
diff --git a/llvm/test/CodeGen/X86/vaargs-win32.ll b/llvm/test/CodeGen/X86/vaargs-win32.ll
index efe6805f928cc..d10b419f6922a 100644
--- a/llvm/test/CodeGen/X86/vaargs-win32.ll
+++ b/llvm/test/CodeGen/X86/vaargs-win32.ll
@@ -34,11 +34,11 @@ entry:
ret void
}
-define <4 x i32> @foo(<4 x float> %0, ...) nounwind {
+define <4 x i32> @foo(<4 x float> inreg %0, ...) nounwind {
; MSVC-LABEL: foo:
; MSVC: # %bb.0:
; MSVC-NEXT: pushl %eax
-; MSVC-NEXT: movaps 8(%esp), %xmm0
+; MSVC-NEXT: movups 8(%esp), %xmm0
; MSVC-NEXT: movups 24(%esp), %xmm1
; MSVC-NEXT: cmpltps %xmm1, %xmm0
; MSVC-NEXT: popl %eax
@@ -73,9 +73,9 @@ define <4 x i32> @bar() nounwind {
; MSVC: # %bb.0:
; MSVC-NEXT: subl $32, %esp
; MSVC-NEXT: movaps {{.*#+}} xmm0 = [5.0E+0,6.0E+0,7.0E+0,8.0E+0]
-; MSVC-NEXT: movaps %xmm0, 16(%esp)
+; MSVC-NEXT: movups %xmm0, 16(%esp)
; MSVC-NEXT: movaps {{.*#+}} xmm0 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
-; MSVC-NEXT: movaps %xmm0, (%esp)
+; MSVC-NEXT: movups %xmm0, (%esp)
; MSVC-NEXT: calll _foo
; MSVC-NEXT: addl $32, %esp
; MSVC-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/win32-spill-xmm.ll b/llvm/test/CodeGen/X86/win32-spill-xmm.ll
index 0ab87a751e4bf..aed4294ef9d1c 100644
--- a/llvm/test/CodeGen/X86/win32-spill-xmm.ll
+++ b/llvm/test/CodeGen/X86/win32-spill-xmm.ll
@@ -4,7 +4,7 @@
; CHECK-LABEL: spill_ok
; CHECK: subl $32, %esp
-; CHECK: movaps %xmm3, (%esp)
+; CHECK: movups %xmm3, (%esp)
; CHECK: movl $0, 16(%esp)
; CHECK: calll _bar
define void @spill_ok(i32, <16 x float> *) {
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