[PATCH] D114642: [AArch64][SchedModels] Handle virtual registers in FP/NEON predicates

[Pavel Kosov via Phabricator via llvm-commits]

kpdev42 updated this revision to Diff 407861.
kpdev42 added a comment.

@dmgreen

> Is it possible to a better example? COPY instructions (especially no-op copys like these) are often expected to be removed by reg-alloc and any scheduling info you give them is likely misleading.”

Well, after some further studying of Exynos M5 model the only instruction group where Q-Form predicate us used is FMINV/FMAXV/FMAXNMV/FMINNMV:

  def : InstRW<[M5WriteNEONZ],  (instregex "^F(MAX|MIN)(NM)?Vv")>;

Q-Form of these instructions can be detected by operand 1, not operand 0. For instance default write resource for “fmaxv h0, v1.4h” is WriteVd and WriteVq for “fmaxv s0, v1.4s”. That’s why we’re now scanning all operands instead of just operand 0 (and both isFpOrNeon and isQForm can probably be considered general). See updated test case. Thank you!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D114642/new/

https://reviews.llvm.org/D114642

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/AArch64/AArch64SchedPredExynos.td
  llvm/lib/Target/AArch64/AArch64SchedPredicates.td
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
  llvm/test/CodeGen/AArch64/misched-predicate-virtreg.mir

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