[llvm] 9fe8a74 - [TableGen] Dump RC.Allocatable with -register-info-debug
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 11 06:07:42 PST 2022
Author: Jay Foad
Date: 2022-02-11T14:07:19Z
New Revision: 9fe8a74c432b9aaee9ac5c33be7ef11b11420427
URL: https://github.com/llvm/llvm-project/commit/9fe8a74c432b9aaee9ac5c33be7ef11b11420427
DIFF: https://github.com/llvm/llvm-project/commit/9fe8a74c432b9aaee9ac5c33be7ef11b11420427.diff
LOG: [TableGen] Dump RC.Allocatable with -register-info-debug
Added:
Modified:
llvm/utils/TableGen/RegisterInfoEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
index d753df1695564..ecbb61806d4ad 100644
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1717,6 +1717,7 @@ void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n';
OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n';
OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n';
+ OS << "\tAllocatable: " << RC.Allocatable << '\n';
OS << "\tRegs:";
for (const CodeGenRegister *R : RC.getMembers()) {
OS << " " << R->getName();
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