[PATCH] D111497: m68k: Support bit shifts on 64-bit integers

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:3261
+  //   Lo = Lo << Shamt
+  //   Hi = (Hi << Shamt) | ((Lo >>u 1) >>u (register size - Shamt))
+  // else:
----------------
"register size - ShAmt" -> "register size - 1 - ShAmt" right?


================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:3272
+      DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize);
+  SDValue RegisterSizeMinus1Shamt =
+      DAG.getNode(ISD::SUB, DL, VT, RegisterSizeMinus1, Shamt);
----------------
This sub can be an xor. See D119411

 I don't m68k, does it have an xor with immediate instruction?


================
Comment at: llvm/lib/Target/M68k/M68kISelLowering.cpp:3289
+
+  SDValue Parts[2] = {Lo, Hi};
+  return DAG.getMergeValues(Parts, DL);
----------------
This temporary array is unnecessary. You can write

```
return DAG.getMergeValues({Lo, Hi}, DL);
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111497/new/

https://reviews.llvm.org/D111497