[llvm] aca355a - [InstCombine] Extend fold (icmp sgt smin(PosA, B) 0) -> (icmp sgt B 0) to support smin intrinsic

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-02-10T13:28:15Z
New Revision: aca355a3bb9917b7e47cf7dc04ad7a96dfa0d43d

URL: https://github.com/llvm/llvm-project/commit/aca355a3bb9917b7e47cf7dc04ad7a96dfa0d43d
DIFF: https://github.com/llvm/llvm-project/commit/aca355a3bb9917b7e47cf7dc04ad7a96dfa0d43d.diff

LOG: [InstCombine] Extend fold (icmp sgt smin(PosA, B) 0) -> (icmp sgt B 0) to support smin intrinsic

Replace matchSelectPattern pattern match with the more general m_SMin so that it can handle smin intrinsics as well as the icmp+select pattern

Noticed while reviewing regressions from D98152

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
    llvm/test/Transforms/InstCombine/min-positive.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index e45be5745fccd..5a6373c0bf3b7 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -1376,8 +1376,7 @@ Instruction *InstCombinerImpl::foldICmpWithZero(ICmpInst &Cmp) {
   // (icmp sgt smin(PosA, B) 0) -> (icmp sgt B 0)
   if (Pred == ICmpInst::ICMP_SGT) {
     Value *A, *B;
-    SelectPatternResult SPR = matchSelectPattern(Cmp.getOperand(0), A, B);
-    if (SPR.Flavor == SPF_SMIN) {
+    if (match(Cmp.getOperand(0), m_SMin(m_Value(A), m_Value(B)))) {
       if (isKnownPositive(A, DL, 0, &AC, &Cmp, &DT))
         return new ICmpInst(Pred, B, Cmp.getOperand(1));
       if (isKnownPositive(B, DL, 0, &AC, &Cmp, &DT))

diff  --git a/llvm/test/Transforms/InstCombine/min-positive.ll b/llvm/test/Transforms/InstCombine/min-positive.ll
index 83628f3ec0c39..572c9ecee71da 100644
--- a/llvm/test/Transforms/InstCombine/min-positive.ll
+++ b/llvm/test/Transforms/InstCombine/min-positive.ll
@@ -15,12 +15,9 @@ define i1 @smin(i32 %other) {
   ret i1 %test
 }
 
-; FIXME: Add intrinsic handling
 define i1 @smin_int(i32 %other) {
 ; CHECK-LABEL: @smin_int(
-; CHECK-NEXT:    [[POSITIVE:%.*]] = load i32, i32* @g, align 4, !range [[RNG0:![0-9]+]]
-; CHECK-NEXT:    [[SMIN:%.*]] = call i32 @llvm.smin.i32(i32 [[POSITIVE]], i32 [[OTHER:%.*]])
-; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt i32 [[SMIN]], 0
+; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt i32 [[OTHER:%.*]], 0
 ; CHECK-NEXT:    ret i1 [[TEST]]
 ;
   %positive = load i32, i32* @g, !range !{i32 1, i32 2048}
@@ -86,7 +83,7 @@ define <2 x i1> @smin_commute_vec_undef_elts(<2 x i32> %x, <2 x i32> %other) {
 
 define i1 @maybe_not_positive(i32 %other) {
 ; CHECK-LABEL: @maybe_not_positive(
-; CHECK-NEXT:    [[POSITIVE:%.*]] = load i32, i32* @g, align 4, !range [[RNG1:![0-9]+]]
+; CHECK-NEXT:    [[POSITIVE:%.*]] = load i32, i32* @g, align 4, !range [[RNG0:![0-9]+]]
 ; CHECK-NEXT:    [[CMP:%.*]] = icmp slt i32 [[POSITIVE]], [[OTHER:%.*]]
 ; CHECK-NEXT:    [[SEL:%.*]] = select i1 [[CMP]], i32 [[POSITIVE]], i32 [[OTHER]]
 ; CHECK-NEXT:    [[TEST:%.*]] = icmp sgt i32 [[SEL]], 0