[PATCH] D119424: [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17200-17201
+// (vselect (p) (a) (op (a) (b))) => (vselect (!p) (op (a) (b)) (a))
+static Optional<SDValue> tryInvertVSelectWithSetCC(SDNode *N,
+                                                   SelectionDAG &DAG) {
+  SDValue SetCC = N->getOperand(0);
----------------
bsmith wrote:
> I believe this transform would loop given something like:
> 
> ```
> m = fmul a, b
> p = setcc <cond> m, 0
> vselect p, m, m
> ```
isnt `vselect p, m, m` a nop?

i've created a test for the example which doesn't loop

```define <vscale x 4 x float> @fcmp_select_f32_double_op(<vscale x 4 x float> %a, <vscale x 4 x float> %b) {
; CHECK-LABEL: fcmp_select_f32_double_op:
; CHECK:       // %bb.0:
; CHECK-NEXT:    fmul z0.s, z0.s, z1.s
; CHECK-NEXT:    ret
  %m = fmul <vscale x 4 x float> %a, %b
  %fcmp = fcmp oeq <vscale x 4 x float> %m, zeroinitializer
  %sel = select <vscale x 4 x i1> %fcmp, <vscale x 4 x float> %m, <vscale x 4 x float> %m
  ret <vscale x 4 x float> %sel
}
```


Repository:
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  https://reviews.llvm.org/D119424/new/

https://reviews.llvm.org/D119424