[PATCH] D119424: [AArch64][SVE] Invert VSelect operand order and condition for predicated arithmetic operations

[Bradley Smith via Phabricator via llvm-commits]

bsmith added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17200-17201
+// (vselect (p) (a) (op (a) (b))) => (vselect (!p) (op (a) (b)) (a))
+static Optional<SDValue> tryInvertVSelectWithSetCC(SDNode *N,
+                                                   SelectionDAG &DAG) {
+  SDValue SetCC = N->getOperand(0);
----------------
I believe this transform would loop given something like:

```
m = fmul a, b
p = setcc <cond> m, 0
vselect p, m, m
```


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:17204
+  if (SetCC.getOpcode() != ISD::SETCC ||
+      SetCC.getOperand(0) != N->getOperand(1))
+    return None;
----------------
The comment above describing this transform isn't accurate as it doesn't reflect these restrictions around setcc.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119424/new/

https://reviews.llvm.org/D119424