[PATCH] D119039: [RISCV] Lower the shufflevector equivalent of vector.splice

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 407236.
craig.topper added a comment.

Switch back to X86's implementation of returning -1.

Returning 0 could be misinterpreted as an identify rotation. So use to be more clear.

The previously identified bug where I returned -1 was hidden because the result
was casted to int in the caller so it failed the > 0 check in the caller.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119039/new/

https://reviews.llvm.org/D119039

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

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