[PATCH] D119302: [AMDGPU] Missed sign/zero extend patterns for divergence-driven instruction selection

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  llc -march=amdgcn  < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s
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File is executable.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119302/new/

https://reviews.llvm.org/D119302