[PATCH] D119196: [RISCV][VP] Lower VP_FMA to RVV instructions.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

In D119196#3308046 <https://reviews.llvm.org/D119196#3308046>, @craig.topper wrote:

> In D119196#3307359 <https://reviews.llvm.org/D119196#3307359>, @frasercrmck wrote:
>
>> Now that D118810 <https://reviews.llvm.org/D118810> landed, I think we can rebase this and switch `true_mask` patterns to use `V0` and rely on the post-process step to select the unmasked FMAs. You'll need to add the mask information to the ternary pseudos, by subclassing them from 
>> `RISCVMaskedPseudo`.  Hopefully that should cut down on the net pattern gain.
>
> The existing operand copying rules in the post-process don't work for FMAs. We need to retain the merge operand during the conversion and I'm not sure how to detect that yet.. Can I do it as a follow up?

Oh yes I missed that: no worries. I didn't mean it to be a must-have. I'm sure we can tackle it later.

LGTM.



================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:1178
+                 (vti.Mask V0), GPR:$vl, vti.Log2SEW)>;
+  // Scalable length vector splats
+  def : Pat<(vti.Vector (riscv_fma_vl (SplatPat vti.ScalarRegClass:$rs1),
----------------
Hopefully this could be improved by D117670?


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