[PATCH] D119110: [RISCV] support vwmulsu_vx when one input is a scalar splat

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7625
 
-    if (IsSignExt) {
+    if (IsSignExt && ISD::isZEXTLoad(Op1.getNode())) {
+      APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize);
----------------
Chenbing.Zheng wrote:
> frasercrmck wrote:
> > The description says that we're now supporting scalar splats but AFAICT this will only work for zero-extending loads? Feels like maybe the testing you're adding is too narrowly-focused and dependent on the `load`.
> I aggre with you. I am sorry about that I have no more ideal about other cases now. May I add a 'Fix me' here ?
Something like this should work.

```
define <8 x i16> @vwmulsu_vx_v8i16_i8(<8 x i8>* %x, i16 %b) {
  %a = load <8 x i8>, <8 x i8>* %x
  %c = and i16 %b, 255
  %d = insertelement <8 x i16> poison, i16 %c, i32 0
  %e = shufflevector <8 x i16> %d, <8 x i16> poison, <8 x i32> zeroinitializer
  %f = sext <8 x i8> %a to <8 x i16>
  %g = mul <8 x i16> %e, %f
  ret <8 x i16> %g
}
```


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D119110/new/

https://reviews.llvm.org/D119110