[PATCH] D119110: [RISCV] support vwmulsu_vx when one input is a scalar splat

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7625
 
-    if (IsSignExt) {
+    if (IsSignExt && ISD::isZEXTLoad(Op1.getNode())) {
+      APInt Mask = APInt::getBitsSetFrom(ScalarBits, NarrowSize);
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frasercrmck wrote:
> The description says that we're now supporting scalar splats but AFAICT this will only work for zero-extending loads? Feels like maybe the testing you're adding is too narrowly-focused and dependent on the `load`.
I aggre with you. I am sorry about that I have no more ideal about other cases now. May I add a 'Fix me' here ?


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  https://reviews.llvm.org/D119110/new/

https://reviews.llvm.org/D119110