[llvm] f21dd70 - [AArch64] Add some additional tests for conditions of branches. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 8 02:28:39 PST 2022
Author: David Green
Date: 2022-02-08T10:28:33Z
New Revision: f21dd70f689071f26d42f36ad15a0ecfb119812a
URL: https://github.com/llvm/llvm-project/commit/f21dd70f689071f26d42f36ad15a0ecfb119812a
DIFF: https://github.com/llvm/llvm-project/commit/f21dd70f689071f26d42f36ad15a0ecfb119812a.diff
LOG: [AArch64] Add some additional tests for conditions of branches. NFC
Added:
llvm/test/CodeGen/AArch64/andorbrcompare.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/andorbrcompare.ll b/llvm/test/CodeGen/AArch64/andorbrcompare.ll
new file mode 100644
index 0000000000000..86b41e893dfbd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/andorbrcompare.ll
@@ -0,0 +1,260 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs %s -o - | FileCheck %s
+
+declare void @dummy()
+
+define i32 @and_eq_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_eq_ne_ult:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #4, eq
+; CHECK-NEXT: b.ne .LBB0_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.lo .LBB0_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB0_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp eq i32 %s0, %s1
+ %c1 = icmp ne i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp ult i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_ne_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_ne_ult_ule:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #2, ne
+; CHECK-NEXT: b.lo .LBB1_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.ls .LBB1_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB1_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp ne i32 %s0, %s1
+ %c1 = icmp ult i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp ule i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_ult_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_ult_ule_ugt:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #2, lo
+; CHECK-NEXT: b.ls .LBB2_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.hi .LBB2_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB2_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp ult i32 %s0, %s1
+ %c1 = icmp ule i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp ugt i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_ule_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_ule_ugt_uge:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #0, ls
+; CHECK-NEXT: b.hi .LBB3_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.hs .LBB3_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB3_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp ule i32 %s0, %s1
+ %c1 = icmp ugt i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp uge i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_ugt_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_ugt_uge_slt:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #0, hi
+; CHECK-NEXT: b.hs .LBB4_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.lt .LBB4_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp ugt i32 %s0, %s1
+ %c1 = icmp uge i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp slt i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_uge_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_uge_slt_sle:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #0, hs
+; CHECK-NEXT: b.lt .LBB5_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.le .LBB5_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB5_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp uge i32 %s0, %s1
+ %c1 = icmp slt i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp sle i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_slt_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_slt_sle_sgt:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #0, lt
+; CHECK-NEXT: b.le .LBB6_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.gt .LBB6_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB6_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp slt i32 %s0, %s1
+ %c1 = icmp sle i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp sgt i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
+
+define i32 @and_sle_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3, i32 %s4, i32 %s5, i32* %p) {
+; CHECK-LABEL: and_sle_sgt_sge:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: cmp w0, w1
+; CHECK-NEXT: ccmp w2, w3, #4, le
+; CHECK-NEXT: b.gt .LBB7_3
+; CHECK-NEXT: // %bb.1: // %entry
+; CHECK-NEXT: cmp w4, w5
+; CHECK-NEXT: b.ge .LBB7_3
+; CHECK-NEXT: // %bb.2:
+; CHECK-NEXT: mov w0, wzr
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB7_3: // %if
+; CHECK-NEXT: mov w0, #1
+; CHECK-NEXT: str w0, [x6]
+; CHECK-NEXT: ret
+entry:
+ %c0 = icmp sle i32 %s0, %s1
+ %c1 = icmp sgt i32 %s2, %s3
+ %a = and i1 %c0, %c1
+ %c2 = icmp sge i32 %s4, %s5
+ %o = or i1 %a, %c2
+ br i1 %o, label %if, label %else
+
+if:
+ store i32 1, i32* %p
+ ret i32 1
+
+else:
+ ret i32 0
+}
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