[llvm] 1d8bbe3 - [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Feb 4 10:44:02 PST 2022
Author: Craig Topper
Date: 2022-02-04T10:43:46-08:00
New Revision: 1d8bbe3d255ff5fa3e0049922398f7e2f3662827
URL: https://github.com/llvm/llvm-project/commit/1d8bbe3d255ff5fa3e0049922398f7e2f3662827
DIFF: https://github.com/llvm/llvm-project/commit/1d8bbe3d255ff5fa3e0049922398f7e2f3662827.diff
LOG: [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
Using AArch64's original implementation for reference, this patch
implements a pass to remove unneeded copies of X0. This pass runs
after register allocation and looks to see if a register is implied
to be 0 by a branch in the predecessor basic block.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D118160
Added:
llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
Modified:
llvm/lib/Target/RISCV/CMakeLists.txt
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/test/CodeGen/RISCV/double-convert.ll
llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
llvm/test/CodeGen/RISCV/float-convert.ll
llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
llvm/test/CodeGen/RISCV/fpclamptosat.ll
llvm/test/CodeGen/RISCV/half-convert.ll
llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/CMakeLists.txt b/llvm/lib/Target/RISCV/CMakeLists.txt
index d1b0863d439b..aa02237c3473 100644
--- a/llvm/lib/Target/RISCV/CMakeLists.txt
+++ b/llvm/lib/Target/RISCV/CMakeLists.txt
@@ -33,6 +33,7 @@ add_llvm_target(RISCVCodeGen
RISCVLegalizerInfo.cpp
RISCVMCInstLower.cpp
RISCVMergeBaseOffset.cpp
+ RISCVRedundantCopyElimination.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterInfo.cpp
RISCVSExtWRemoval.cpp
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 03462240fd93..9d8290f750bf 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -55,6 +55,9 @@ void initializeRISCVExpandAtomicPseudoPass(PassRegistry &);
FunctionPass *createRISCVInsertVSETVLIPass();
void initializeRISCVInsertVSETVLIPass(PassRegistry &);
+FunctionPass *createRISCVRedundantCopyEliminationPass();
+void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
+
InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
RISCVSubtarget &,
RISCVRegisterBankInfo &);
diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
new file mode 100644
index 000000000000..3c4a60b81d8e
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -0,0 +1,179 @@
+//=- RISCVRedundantCopyElimination.cpp - Remove useless copy for RISCV ------=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass removes unnecessary zero copies in BBs that are targets of
+// beqz/bnez instructions. For instance, the copy instruction in the code below
+// can be removed because the beqz jumps to BB#2 when a0 is zero.
+// BB#1:
+// beqz %a0, <BB#2>
+// BB#2:
+// %a0 = COPY %x0
+// This pass should be run after register allocation.
+//
+// This pass is based on the earliest versions of
+// AArch64RedundantCopyElimination.
+//
+// FIXME: Support compares with constants other than zero? This is harder to
+// do on RISC-V since branches can't have immediates.
+//
+//===----------------------------------------------------------------------===//
+
+#include "RISCV.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/Support/Debug.h"
+
+using namespace llvm;
+
+#define DEBUG_TYPE "riscv-copyelim"
+
+STATISTIC(NumCopiesRemoved, "Number of copies removed.");
+
+namespace {
+class RISCVRedundantCopyElimination : public MachineFunctionPass {
+ const MachineRegisterInfo *MRI;
+ const TargetRegisterInfo *TRI;
+
+public:
+ static char ID;
+ RISCVRedundantCopyElimination() : MachineFunctionPass(ID) {
+ initializeRISCVRedundantCopyEliminationPass(
+ *PassRegistry::getPassRegistry());
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoVRegs);
+ }
+
+ StringRef getPassName() const override {
+ return "RISCV Redundant Copy Elimination";
+ }
+
+private:
+ bool optimizeBlock(MachineBasicBlock &MBB);
+};
+
+} // end anonymous namespace
+
+char RISCVRedundantCopyElimination::ID = 0;
+
+INITIALIZE_PASS(RISCVRedundantCopyElimination, "riscv-copyelim",
+ "RISCV redundant copy elimination pass", false, false)
+
+static bool guaranteesZeroRegInBlock(const MachineInstr &MI,
+ const MachineBasicBlock &MBB) {
+ unsigned Opc = MI.getOpcode();
+ if (Opc == RISCV::BEQ && MI.getOperand(1).getReg() == RISCV::X0 &&
+ &MBB == MI.getOperand(2).getMBB())
+ return true;
+ if (Opc == RISCV::BNE && MI.getOperand(1).getReg() == RISCV::X0 &&
+ &MBB != MI.getOperand(2).getMBB())
+ return true;
+
+ return false;
+}
+
+bool RISCVRedundantCopyElimination::optimizeBlock(MachineBasicBlock &MBB) {
+ // Check if the current basic block has a single predecessor.
+ if (MBB.pred_size() != 1)
+ return false;
+
+ // Check if the predecessor has two successors, implying the block ends in a
+ // conditional branch.
+ MachineBasicBlock *PredMBB = *MBB.pred_begin();
+ if (PredMBB->succ_size() != 2)
+ return false;
+
+ MachineBasicBlock::iterator CondBr = PredMBB->getLastNonDebugInstr();
+ if (CondBr == PredMBB->end())
+ return false;
+
+ while (true) {
+ // If we run out of terminators, give up.
+ if (!CondBr->isTerminator())
+ return false;
+ // If we found a branch with X0, stop searching and try to remove copies.
+ // TODO: Handle multiple branches with
diff erent registers.
+ if (guaranteesZeroRegInBlock(*CondBr, MBB))
+ break;
+ // If we reached the beginning of the basic block, give up.
+ if (CondBr == PredMBB->begin())
+ return false;
+ --CondBr;
+ }
+
+ Register TargetReg = CondBr->getOperand(0).getReg();
+ if (!TargetReg)
+ return false;
+
+ bool Changed = false;
+ MachineBasicBlock::iterator LastChange = MBB.begin();
+ // Remove redundant Copy instructions unless TargetReg is modified.
+ for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;) {
+ MachineInstr *MI = &*I;
+ ++I;
+ if (MI->isCopy() && MI->getOperand(0).isReg() &&
+ MI->getOperand(1).isReg()) {
+ Register DefReg = MI->getOperand(0).getReg();
+ Register SrcReg = MI->getOperand(1).getReg();
+
+ if (SrcReg == RISCV::X0 && !MRI->isReserved(DefReg) &&
+ TargetReg == DefReg) {
+ LLVM_DEBUG(dbgs() << "Remove redundant Copy : ");
+ LLVM_DEBUG(MI->print(dbgs()));
+
+ MI->eraseFromParent();
+ Changed = true;
+ LastChange = I;
+ ++NumCopiesRemoved;
+ continue;
+ }
+ }
+
+ if (MI->modifiesRegister(TargetReg, TRI))
+ break;
+ }
+
+ if (!Changed)
+ return false;
+
+ // Otherwise, we have to fixup the use-def chain, starting with the
+ // BEQ/BNE. Conservatively mark as much as we can live.
+ CondBr->clearRegisterKills(TargetReg, TRI);
+
+ // Add newly used reg to the block's live-in list if it isn't there already.
+ if (!MBB.isLiveIn(TargetReg))
+ MBB.addLiveIn(TargetReg);
+
+ // Clear any kills of TargetReg between CondBr and the last removed COPY.
+ for (MachineInstr &MMI : make_range(MBB.begin(), LastChange))
+ MMI.clearRegisterKills(TargetReg, TRI);
+
+ return true;
+}
+
+bool RISCVRedundantCopyElimination::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+
+ TRI = MF.getSubtarget().getRegisterInfo();
+ MRI = &MF.getRegInfo();
+
+ bool Changed = false;
+ for (MachineBasicBlock &MBB : MF)
+ Changed |= optimizeBlock(MBB);
+
+ return Changed;
+}
+
+FunctionPass *llvm::createRISCVRedundantCopyEliminationPass() {
+ return new RISCVRedundantCopyElimination();
+}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index db5e2f1eeb6f..77cc9ee535d2 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -32,6 +32,11 @@
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
+static cl::opt<bool> EnableRedundantCopyElimination(
+ "riscv-enable-copyelim",
+ cl::desc("Enable the redundant copy elimination pass"), cl::init(true),
+ cl::Hidden);
+
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -143,6 +148,7 @@ class RISCVPassConfig : public TargetPassConfig {
void addPreSched2() override;
void addMachineSSAOptimization() override;
void addPreRegAlloc() override;
+ void addPostRegAlloc() override;
};
} // namespace
@@ -208,3 +214,8 @@ void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass());
}
+
+void RISCVPassConfig::addPostRegAlloc() {
+ if (TM->getOptLevel() != CodeGenOpt::None && EnableRedundantCopyElimination)
+ addPass(createRISCVRedundantCopyEliminationPass());
+}
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
index 4cae4e16b449..46fb6cd9e52d 100644
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -108,23 +108,19 @@ define i32 @fcvt_w_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB3_2
-; RV32IFD-NEXT: # %bb.1: # %start
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB3_2:
+; RV32IFD-NEXT: beqz a0, .LBB3_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT: .LBB3_2: # %start
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_w_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB3_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB3_2:
+; RV64IFD-NEXT: beqz a0, .LBB3_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB3_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_d_sat:
@@ -335,23 +331,19 @@ define i32 @fcvt_wu_d_sat(double %a) nounwind {
; RV32IFD-LABEL: fcvt_wu_d_sat:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB6_2
-; RV32IFD-NEXT: # %bb.1: # %start
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB6_2:
+; RV32IFD-NEXT: beqz a0, .LBB6_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT: .LBB6_2: # %start
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_wu_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB6_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB6_2:
+; RV64IFD-NEXT: beqz a0, .LBB6_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB6_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_d_sat:
@@ -674,12 +666,10 @@ define i64 @fcvt_l_d_sat(double %a) nounwind {
; RV64IFD-LABEL: fcvt_l_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB12_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB12_2:
+; RV64IFD-NEXT: beqz a0, .LBB12_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB12_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_l_d_sat:
@@ -916,12 +906,10 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind {
; RV64IFD-LABEL: fcvt_lu_d_sat:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB14_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB14_2:
+; RV64IFD-NEXT: beqz a0, .LBB14_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB14_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_lu_d_sat:
@@ -1475,11 +1463,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i16:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB26_2
-; RV32IFD-NEXT: # %bb.1: # %start
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB26_2:
+; RV32IFD-NEXT: beqz a0, .LBB26_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI26_1)
@@ -1487,16 +1472,14 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB26_2: # %start
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_w_s_sat_i16:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB26_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB26_2:
+; RV64IFD-NEXT: beqz a0, .LBB26_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI26_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI26_1)
@@ -1504,6 +1487,7 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: .LBB26_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -1793,11 +1777,8 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32IFD-LABEL: fcvt_w_s_sat_i8:
; RV32IFD: # %bb.0: # %start
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB30_2
-; RV32IFD-NEXT: # %bb.1: # %start
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB30_2:
+; RV32IFD-NEXT: beqz a0, .LBB30_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV32IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
; RV32IFD-NEXT: lui a0, %hi(.LCPI30_1)
@@ -1805,16 +1786,14 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV32IFD-NEXT: fmax.d ft0, fa0, ft0
; RV32IFD-NEXT: fmin.d ft0, ft0, ft1
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB30_2: # %start
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fcvt_w_s_sat_i8:
; RV64IFD: # %bb.0: # %start
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB30_2
-; RV64IFD-NEXT: # %bb.1: # %start
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB30_2:
+; RV64IFD-NEXT: beqz a0, .LBB30_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_0)
; RV64IFD-NEXT: fld ft0, %lo(.LCPI30_0)(a0)
; RV64IFD-NEXT: lui a0, %hi(.LCPI30_1)
@@ -1822,6 +1801,7 @@ define signext i8 @fcvt_w_s_sat_i8(double %a) nounwind {
; RV64IFD-NEXT: fmax.d ft0, fa0, ft0
; RV64IFD-NEXT: fmin.d ft0, ft0, ft1
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: .LBB30_2: # %start
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
index 38d82f6e46ff..022705474451 100644
--- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
@@ -8,23 +8,19 @@ define signext i32 @test_floor_si32(double %x) {
; RV32IFD-LABEL: test_floor_si32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB0_2
+; RV32IFD-NEXT: beqz a0, .LBB0_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB0_2:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rdn
+; RV32IFD-NEXT: .LBB0_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_floor_si32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB0_2
+; RV64IFD-NEXT: beqz a0, .LBB0_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB0_2:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rdn
+; RV64IFD-NEXT: .LBB0_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -91,12 +87,10 @@ define i64 @test_floor_si64(double %x) nounwind {
; RV64IFD-LABEL: test_floor_si64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB1_2
+; RV64IFD-NEXT: beqz a0, .LBB1_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB1_2:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rdn
+; RV64IFD-NEXT: .LBB1_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -107,23 +101,19 @@ define signext i32 @test_floor_ui32(double %x) {
; RV32IFD-LABEL: test_floor_ui32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB2_2
+; RV32IFD-NEXT: beqz a0, .LBB2_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB2_2:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rdn
+; RV32IFD-NEXT: .LBB2_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_floor_ui32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB2_2
+; RV64IFD-NEXT: beqz a0, .LBB2_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB2_2:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rdn
+; RV64IFD-NEXT: .LBB2_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
@@ -177,12 +167,10 @@ define i64 @test_floor_ui64(double %x) nounwind {
; RV64IFD-LABEL: test_floor_ui64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB3_2
+; RV64IFD-NEXT: beqz a0, .LBB3_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rdn
+; RV64IFD-NEXT: .LBB3_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.floor.f64(double %x)
%b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
@@ -193,23 +181,19 @@ define signext i32 @test_ceil_si32(double %x) {
; RV32IFD-LABEL: test_ceil_si32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB4_2
+; RV32IFD-NEXT: beqz a0, .LBB4_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB4_2:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rup
+; RV32IFD-NEXT: .LBB4_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_ceil_si32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB4_2
+; RV64IFD-NEXT: beqz a0, .LBB4_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rup
+; RV64IFD-NEXT: .LBB4_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -276,12 +260,10 @@ define i64 @test_ceil_si64(double %x) nounwind {
; RV64IFD-LABEL: test_ceil_si64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB5_2
+; RV64IFD-NEXT: beqz a0, .LBB5_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB5_2:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rup
+; RV64IFD-NEXT: .LBB5_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -292,23 +274,19 @@ define signext i32 @test_ceil_ui32(double %x) {
; RV32IFD-LABEL: test_ceil_ui32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB6_2
+; RV32IFD-NEXT: beqz a0, .LBB6_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB6_2:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rup
+; RV32IFD-NEXT: .LBB6_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_ceil_ui32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB6_2
+; RV64IFD-NEXT: beqz a0, .LBB6_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB6_2:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rup
+; RV64IFD-NEXT: .LBB6_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
@@ -362,12 +340,10 @@ define i64 @test_ceil_ui64(double %x) nounwind {
; RV64IFD-LABEL: test_ceil_ui64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB7_2
+; RV64IFD-NEXT: beqz a0, .LBB7_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB7_2:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rup
+; RV64IFD-NEXT: .LBB7_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.ceil.f64(double %x)
%b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
@@ -378,23 +354,19 @@ define signext i32 @test_trunc_si32(double %x) {
; RV32IFD-LABEL: test_trunc_si32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB8_2
+; RV32IFD-NEXT: beqz a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rtz
+; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_trunc_si32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB8_2
+; RV64IFD-NEXT: beqz a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB8_2:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB8_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -461,12 +433,10 @@ define i64 @test_trunc_si64(double %x) nounwind {
; RV64IFD-LABEL: test_trunc_si64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB9_2
+; RV64IFD-NEXT: beqz a0, .LBB9_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB9_2:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB9_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -477,23 +447,19 @@ define signext i32 @test_trunc_ui32(double %x) {
; RV32IFD-LABEL: test_trunc_ui32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB10_2
+; RV32IFD-NEXT: beqz a0, .LBB10_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB10_2:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; RV32IFD-NEXT: .LBB10_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_trunc_ui32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB10_2
+; RV64IFD-NEXT: beqz a0, .LBB10_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB10_2:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB10_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
@@ -547,12 +513,10 @@ define i64 @test_trunc_ui64(double %x) nounwind {
; RV64IFD-LABEL: test_trunc_ui64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB11_2
+; RV64IFD-NEXT: beqz a0, .LBB11_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB11_2:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rtz
+; RV64IFD-NEXT: .LBB11_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.trunc.f64(double %x)
%b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
@@ -563,23 +527,19 @@ define signext i32 @test_round_si32(double %x) {
; RV32IFD-LABEL: test_round_si32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB12_2
+; RV32IFD-NEXT: beqz a0, .LBB12_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB12_2:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rmm
+; RV32IFD-NEXT: .LBB12_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_round_si32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB12_2
+; RV64IFD-NEXT: beqz a0, .LBB12_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB12_2:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rmm
+; RV64IFD-NEXT: .LBB12_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -646,12 +606,10 @@ define i64 @test_round_si64(double %x) nounwind {
; RV64IFD-LABEL: test_round_si64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB13_2
+; RV64IFD-NEXT: beqz a0, .LBB13_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB13_2:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rmm
+; RV64IFD-NEXT: .LBB13_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -662,23 +620,19 @@ define signext i32 @test_round_ui32(double %x) {
; RV32IFD-LABEL: test_round_ui32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB14_2
+; RV32IFD-NEXT: beqz a0, .LBB14_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB14_2:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rmm
+; RV32IFD-NEXT: .LBB14_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_round_ui32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB14_2
+; RV64IFD-NEXT: beqz a0, .LBB14_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB14_2:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rmm
+; RV64IFD-NEXT: .LBB14_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
@@ -732,12 +686,10 @@ define i64 @test_round_ui64(double %x) nounwind {
; RV64IFD-LABEL: test_round_ui64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB15_2
+; RV64IFD-NEXT: beqz a0, .LBB15_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB15_2:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rmm
+; RV64IFD-NEXT: .LBB15_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.round.f64(double %x)
%b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
@@ -748,23 +700,19 @@ define signext i32 @test_roundeven_si32(double %x) {
; RV32IFD-LABEL: test_roundeven_si32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB16_2
+; RV32IFD-NEXT: beqz a0, .LBB16_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB16_2:
; RV32IFD-NEXT: fcvt.w.d a0, fa0, rne
+; RV32IFD-NEXT: .LBB16_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_roundeven_si32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB16_2
+; RV64IFD-NEXT: beqz a0, .LBB16_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB16_2:
; RV64IFD-NEXT: fcvt.w.d a0, fa0, rne
+; RV64IFD-NEXT: .LBB16_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -831,12 +779,10 @@ define i64 @test_roundeven_si64(double %x) nounwind {
; RV64IFD-LABEL: test_roundeven_si64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB17_2
+; RV64IFD-NEXT: beqz a0, .LBB17_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB17_2:
; RV64IFD-NEXT: fcvt.l.d a0, fa0, rne
+; RV64IFD-NEXT: .LBB17_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -847,23 +793,19 @@ define signext i32 @test_roundeven_ui32(double %x) {
; RV32IFD-LABEL: test_roundeven_ui32:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: feq.d a0, fa0, fa0
-; RV32IFD-NEXT: bnez a0, .LBB18_2
+; RV32IFD-NEXT: beqz a0, .LBB18_2
; RV32IFD-NEXT: # %bb.1:
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB18_2:
; RV32IFD-NEXT: fcvt.wu.d a0, fa0, rne
+; RV32IFD-NEXT: .LBB18_2:
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: test_roundeven_ui32:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB18_2
+; RV64IFD-NEXT: beqz a0, .LBB18_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB18_2:
; RV64IFD-NEXT: fcvt.wu.d a0, fa0, rne
+; RV64IFD-NEXT: .LBB18_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i32 @llvm.fptoui.sat.i32.f64(double %a)
@@ -917,12 +859,10 @@ define i64 @test_roundeven_ui64(double %x) nounwind {
; RV64IFD-LABEL: test_roundeven_ui64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: feq.d a0, fa0, fa0
-; RV64IFD-NEXT: bnez a0, .LBB19_2
+; RV64IFD-NEXT: beqz a0, .LBB19_2
; RV64IFD-NEXT: # %bb.1:
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB19_2:
; RV64IFD-NEXT: fcvt.lu.d a0, fa0, rne
+; RV64IFD-NEXT: .LBB19_2:
; RV64IFD-NEXT: ret
%a = call double @llvm.roundeven.f64(double %x)
%b = call i64 @llvm.fptoui.sat.i64.f64(double %a)
diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll
index ce97b2930e39..97ec565448b0 100644
--- a/llvm/test/CodeGen/RISCV/float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/float-convert.ll
@@ -44,23 +44,19 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB1_2
-; RV32IF-NEXT: # %bb.1: # %start
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB1_2:
+; RV32IF-NEXT: beqz a0, .LBB1_2
+; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
+; RV32IF-NEXT: .LBB1_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_w_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB1_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB1_2:
+; RV64IF-NEXT: beqz a0, .LBB1_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB1_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat:
@@ -256,23 +252,19 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32IF-LABEL: fcvt_wu_s_sat:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB4_2
-; RV32IF-NEXT: # %bb.1: # %start
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB4_2:
+; RV32IF-NEXT: beqz a0, .LBB4_2
+; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT: .LBB4_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_wu_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB4_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB4_2:
+; RV64IF-NEXT: beqz a0, .LBB4_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB4_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_s_sat:
@@ -660,12 +652,10 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64IF-LABEL: fcvt_l_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB12_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB12_2:
+; RV64IF-NEXT: beqz a0, .LBB12_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB12_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_l_s_sat:
@@ -882,12 +872,10 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64IF-LABEL: fcvt_lu_s_sat:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB14_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB14_2:
+; RV64IF-NEXT: beqz a0, .LBB14_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB14_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_lu_s_sat:
@@ -1340,11 +1328,8 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat_i16:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB24_2
-; RV32IF-NEXT: # %bb.1: # %start
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB24_2:
+; RV32IF-NEXT: beqz a0, .LBB24_2
+; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI24_1)
@@ -1352,16 +1337,14 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32IF-NEXT: fmax.s ft0, fa0, ft0
; RV32IF-NEXT: fmin.s ft0, ft0, ft1
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: .LBB24_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_w_s_sat_i16:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB24_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB24_2:
+; RV64IF-NEXT: beqz a0, .LBB24_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI24_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI24_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI24_1)
@@ -1369,6 +1352,7 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64IF-NEXT: fmax.s ft0, fa0, ft0
; RV64IF-NEXT: fmin.s ft0, ft0, ft1
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: .LBB24_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -1636,11 +1620,8 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV32IF-LABEL: fcvt_w_s_sat_i8:
; RV32IF: # %bb.0: # %start
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB28_2
-; RV32IF-NEXT: # %bb.1: # %start
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB28_2:
+; RV32IF-NEXT: beqz a0, .LBB28_2
+; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: lui a0, %hi(.LCPI28_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
; RV32IF-NEXT: lui a0, %hi(.LCPI28_1)
@@ -1648,16 +1629,14 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV32IF-NEXT: fmax.s ft0, fa0, ft0
; RV32IF-NEXT: fmin.s ft0, ft0, ft1
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IF-NEXT: .LBB28_2: # %start
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcvt_w_s_sat_i8:
; RV64IF: # %bb.0: # %start
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB28_2
-; RV64IF-NEXT: # %bb.1: # %start
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB28_2:
+; RV64IF-NEXT: beqz a0, .LBB28_2
+; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: lui a0, %hi(.LCPI28_0)
; RV64IF-NEXT: flw ft0, %lo(.LCPI28_0)(a0)
; RV64IF-NEXT: lui a0, %hi(.LCPI28_1)
@@ -1665,6 +1644,7 @@ define signext i8 @fcvt_w_s_sat_i8(float %a) nounwind {
; RV64IF-NEXT: fmax.s ft0, fa0, ft0
; RV64IF-NEXT: fmin.s ft0, ft0, ft1
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IF-NEXT: .LBB28_2: # %start
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
index 9893b697af29..834b7f72dd66 100644
--- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
@@ -8,23 +8,19 @@ define signext i32 @test_floor_si32(float %x) {
; RV32IF-LABEL: test_floor_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB0_2
+; RV32IF-NEXT: beqz a0, .LBB0_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB0_2:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rdn
+; RV32IF-NEXT: .LBB0_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB0_2
+; RV64IF-NEXT: beqz a0, .LBB0_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB0_2:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rdn
+; RV64IF-NEXT: .LBB0_2:
; RV64IF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -91,12 +87,10 @@ define i64 @test_floor_si64(float %x) nounwind {
; RV64IF-LABEL: test_floor_si64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB1_2
+; RV64IF-NEXT: beqz a0, .LBB1_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB1_2:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rdn
+; RV64IF-NEXT: .LBB1_2:
; RV64IF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -107,23 +101,19 @@ define signext i32 @test_floor_ui32(float %x) {
; RV32IF-LABEL: test_floor_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB2_2
+; RV32IF-NEXT: beqz a0, .LBB2_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB2_2:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rdn
+; RV32IF-NEXT: .LBB2_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_floor_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB2_2
+; RV64IF-NEXT: beqz a0, .LBB2_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB2_2:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rdn
+; RV64IF-NEXT: .LBB2_2:
; RV64IF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -177,12 +167,10 @@ define i64 @test_floor_ui64(float %x) nounwind {
; RV64IF-LABEL: test_floor_ui64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB3_2
+; RV64IF-NEXT: beqz a0, .LBB3_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB3_2:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rdn
+; RV64IF-NEXT: .LBB3_2:
; RV64IF-NEXT: ret
%a = call float @llvm.floor.f32(float %x)
%b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
@@ -193,23 +181,19 @@ define signext i32 @test_ceil_si32(float %x) {
; RV32IF-LABEL: test_ceil_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB4_2
+; RV32IF-NEXT: beqz a0, .LBB4_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rup
+; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB4_2
+; RV64IF-NEXT: beqz a0, .LBB4_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB4_2:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rup
+; RV64IF-NEXT: .LBB4_2:
; RV64IF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -276,12 +260,10 @@ define i64 @test_ceil_si64(float %x) nounwind {
; RV64IF-LABEL: test_ceil_si64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB5_2
+; RV64IF-NEXT: beqz a0, .LBB5_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB5_2:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rup
+; RV64IF-NEXT: .LBB5_2:
; RV64IF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -292,23 +274,19 @@ define signext i32 @test_ceil_ui32(float %x) {
; RV32IF-LABEL: test_ceil_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB6_2
+; RV32IF-NEXT: beqz a0, .LBB6_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB6_2:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rup
+; RV32IF-NEXT: .LBB6_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_ceil_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB6_2
+; RV64IF-NEXT: beqz a0, .LBB6_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB6_2:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rup
+; RV64IF-NEXT: .LBB6_2:
; RV64IF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -362,12 +340,10 @@ define i64 @test_ceil_ui64(float %x) nounwind {
; RV64IF-LABEL: test_ceil_ui64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB7_2
+; RV64IF-NEXT: beqz a0, .LBB7_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB7_2:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rup
+; RV64IF-NEXT: .LBB7_2:
; RV64IF-NEXT: ret
%a = call float @llvm.ceil.f32(float %x)
%b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
@@ -378,23 +354,19 @@ define signext i32 @test_trunc_si32(float %x) {
; RV32IF-LABEL: test_trunc_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB8_2
+; RV32IF-NEXT: beqz a0, .LBB8_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rtz
+; RV32IF-NEXT: .LBB8_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB8_2
+; RV64IF-NEXT: beqz a0, .LBB8_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB8_2:
; RV64IF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -461,12 +433,10 @@ define i64 @test_trunc_si64(float %x) nounwind {
; RV64IF-LABEL: test_trunc_si64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB9_2
+; RV64IF-NEXT: beqz a0, .LBB9_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB9_2:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB9_2:
; RV64IF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -477,23 +447,19 @@ define signext i32 @test_trunc_ui32(float %x) {
; RV32IF-LABEL: test_trunc_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB10_2
+; RV32IF-NEXT: beqz a0, .LBB10_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB10_2:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rtz
+; RV32IF-NEXT: .LBB10_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_trunc_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB10_2
+; RV64IF-NEXT: beqz a0, .LBB10_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB10_2:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB10_2:
; RV64IF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -547,12 +513,10 @@ define i64 @test_trunc_ui64(float %x) nounwind {
; RV64IF-LABEL: test_trunc_ui64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB11_2
+; RV64IF-NEXT: beqz a0, .LBB11_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB11_2:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rtz
+; RV64IF-NEXT: .LBB11_2:
; RV64IF-NEXT: ret
%a = call float @llvm.trunc.f32(float %x)
%b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
@@ -563,23 +527,19 @@ define signext i32 @test_round_si32(float %x) {
; RV32IF-LABEL: test_round_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB12_2
+; RV32IF-NEXT: beqz a0, .LBB12_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB12_2:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rmm
+; RV32IF-NEXT: .LBB12_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB12_2
+; RV64IF-NEXT: beqz a0, .LBB12_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB12_2:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rmm
+; RV64IF-NEXT: .LBB12_2:
; RV64IF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -646,12 +606,10 @@ define i64 @test_round_si64(float %x) nounwind {
; RV64IF-LABEL: test_round_si64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB13_2
+; RV64IF-NEXT: beqz a0, .LBB13_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB13_2:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rmm
+; RV64IF-NEXT: .LBB13_2:
; RV64IF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -662,23 +620,19 @@ define signext i32 @test_round_ui32(float %x) {
; RV32IF-LABEL: test_round_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB14_2
+; RV32IF-NEXT: beqz a0, .LBB14_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB14_2:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rmm
+; RV32IF-NEXT: .LBB14_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_round_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB14_2
+; RV64IF-NEXT: beqz a0, .LBB14_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rmm
+; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -732,12 +686,10 @@ define i64 @test_round_ui64(float %x) nounwind {
; RV64IF-LABEL: test_round_ui64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB15_2
+; RV64IF-NEXT: beqz a0, .LBB15_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB15_2:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rmm
+; RV64IF-NEXT: .LBB15_2:
; RV64IF-NEXT: ret
%a = call float @llvm.round.f32(float %x)
%b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
@@ -748,23 +700,19 @@ define signext i32 @test_roundeven_si32(float %x) {
; RV32IF-LABEL: test_roundeven_si32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB16_2
+; RV32IF-NEXT: beqz a0, .LBB16_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: fcvt.w.s a0, fa0, rne
+; RV32IF-NEXT: .LBB16_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_si32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB16_2
+; RV64IF-NEXT: beqz a0, .LBB16_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB16_2:
; RV64IF-NEXT: fcvt.w.s a0, fa0, rne
+; RV64IF-NEXT: .LBB16_2:
; RV64IF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -831,12 +779,10 @@ define i64 @test_roundeven_si64(float %x) nounwind {
; RV64IF-LABEL: test_roundeven_si64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB17_2
+; RV64IF-NEXT: beqz a0, .LBB17_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB17_2:
; RV64IF-NEXT: fcvt.l.s a0, fa0, rne
+; RV64IF-NEXT: .LBB17_2:
; RV64IF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -847,23 +793,19 @@ define signext i32 @test_roundeven_ui32(float %x) {
; RV32IF-LABEL: test_roundeven_ui32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: feq.s a0, fa0, fa0
-; RV32IF-NEXT: bnez a0, .LBB18_2
+; RV32IF-NEXT: beqz a0, .LBB18_2
; RV32IF-NEXT: # %bb.1:
-; RV32IF-NEXT: li a0, 0
-; RV32IF-NEXT: ret
-; RV32IF-NEXT: .LBB18_2:
; RV32IF-NEXT: fcvt.wu.s a0, fa0, rne
+; RV32IF-NEXT: .LBB18_2:
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: test_roundeven_ui32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB18_2
+; RV64IF-NEXT: beqz a0, .LBB18_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB18_2:
; RV64IF-NEXT: fcvt.wu.s a0, fa0, rne
+; RV64IF-NEXT: .LBB18_2:
; RV64IF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i32 @llvm.fptoui.sat.i32.f32(float %a)
@@ -917,12 +859,10 @@ define i64 @test_roundeven_ui64(float %x) nounwind {
; RV64IF-LABEL: test_roundeven_ui64:
; RV64IF: # %bb.0:
; RV64IF-NEXT: feq.s a0, fa0, fa0
-; RV64IF-NEXT: bnez a0, .LBB19_2
+; RV64IF-NEXT: beqz a0, .LBB19_2
; RV64IF-NEXT: # %bb.1:
-; RV64IF-NEXT: li a0, 0
-; RV64IF-NEXT: ret
-; RV64IF-NEXT: .LBB19_2:
; RV64IF-NEXT: fcvt.lu.s a0, fa0, rne
+; RV64IF-NEXT: .LBB19_2:
; RV64IF-NEXT: ret
%a = call float @llvm.roundeven.f32(float %x)
%b = call i64 @llvm.fptoui.sat.i64.f32(float %a)
diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
index fdbec8d727d5..abf4101badd5 100644
--- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll
+++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll
@@ -77,13 +77,10 @@ define i32 @stest_f64i32(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB0_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB0_2:
+; RV32IFD-NEXT: beqz a0, .LBB0_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB0_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -163,13 +160,10 @@ define i32 @utest_f64i32(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB1_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB1_2:
+; RV32IFD-NEXT: beqz a0, .LBB1_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB1_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -257,13 +251,10 @@ define i32 @ustest_f64i32(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB2_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB2_2:
+; RV32IFD-NEXT: beqz a0, .LBB2_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB2_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -299,12 +290,10 @@ define i32 @stest_f32i32(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB3_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB3_2:
+; RV32-NEXT: beqz a0, .LBB3_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32-NEXT: .LBB3_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: stest_f32i32:
@@ -339,12 +328,10 @@ define i32 @utest_f32i32(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB4_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB4_2:
+; RV32-NEXT: beqz a0, .LBB4_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT: .LBB4_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: utest_f32i32:
@@ -371,12 +358,10 @@ define i32 @ustest_f32i32(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB5_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB5_2:
+; RV32-NEXT: beqz a0, .LBB5_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT: .LBB5_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: ustest_f32i32:
@@ -1257,12 +1242,10 @@ define i64 @stest_f64i64(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
-; RV64IFD-NEXT: bnez a0, .LBB18_2
-; RV64IFD-NEXT: # %bb.1: # %entry
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB18_2:
+; RV64IFD-NEXT: beqz a0, .LBB18_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: .LBB18_2: # %entry
; RV64IFD-NEXT: ret
entry:
%conv = fptosi double %x to i128
@@ -1303,7 +1286,6 @@ define i64 @utest_f64i64(double %x) {
; RV32-NEXT: .LBB19_5: # %entry
; RV32-NEXT: bnez a0, .LBB19_7
; RV32-NEXT: # %bb.6: # %entry
-; RV32-NEXT: li a0, 0
; RV32-NEXT: li a1, 0
; RV32-NEXT: j .LBB19_8
; RV32-NEXT: .LBB19_7:
@@ -1366,7 +1348,6 @@ define i64 @ustest_f64i64(double %x) {
; RV32-NEXT: bnez a1, .LBB20_9
; RV32-NEXT: # %bb.6: # %entry
; RV32-NEXT: li a0, 0
-; RV32-NEXT: li a1, 0
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a3, 1
; RV32-NEXT: bnez a2, .LBB20_10
@@ -1502,12 +1483,10 @@ define i64 @stest_f32i64(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fmv.w.x ft0, a0
; RV64-NEXT: feq.s a0, ft0, ft0
-; RV64-NEXT: bnez a0, .LBB21_2
-; RV64-NEXT: # %bb.1: # %entry
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
-; RV64-NEXT: .LBB21_2:
+; RV64-NEXT: beqz a0, .LBB21_2
+; RV64-NEXT: # %bb.1:
; RV64-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64-NEXT: .LBB21_2: # %entry
; RV64-NEXT: ret
entry:
%conv = fptosi float %x to i128
@@ -1547,7 +1526,6 @@ define i64 @utest_f32i64(float %x) {
; RV32-NEXT: .LBB22_5: # %entry
; RV32-NEXT: bnez a0, .LBB22_7
; RV32-NEXT: # %bb.6: # %entry
-; RV32-NEXT: li a0, 0
; RV32-NEXT: li a1, 0
; RV32-NEXT: j .LBB22_8
; RV32-NEXT: .LBB22_7:
@@ -1609,7 +1587,6 @@ define i64 @ustest_f32i64(float %x) {
; RV32-NEXT: bnez a1, .LBB23_9
; RV32-NEXT: # %bb.6: # %entry
; RV32-NEXT: li a0, 0
-; RV32-NEXT: li a1, 0
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a3, 1
; RV32-NEXT: bnez a2, .LBB23_10
@@ -1818,7 +1795,6 @@ define i64 @utesth_f16i64(half %x) {
; RV32-NEXT: .LBB25_5: # %entry
; RV32-NEXT: bnez a0, .LBB25_7
; RV32-NEXT: # %bb.6: # %entry
-; RV32-NEXT: li a0, 0
; RV32-NEXT: li a1, 0
; RV32-NEXT: j .LBB25_8
; RV32-NEXT: .LBB25_7:
@@ -1882,7 +1858,6 @@ define i64 @ustest_f16i64(half %x) {
; RV32-NEXT: bnez a1, .LBB26_9
; RV32-NEXT: # %bb.6: # %entry
; RV32-NEXT: li a0, 0
-; RV32-NEXT: li a1, 0
; RV32-NEXT: li a2, 0
; RV32-NEXT: li a3, 1
; RV32-NEXT: bnez a2, .LBB26_10
@@ -2042,13 +2017,10 @@ define i32 @stest_f64i32_mm(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB27_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB27_2:
+; RV32IFD-NEXT: beqz a0, .LBB27_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB27_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -2118,13 +2090,10 @@ define i32 @utest_f64i32_mm(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB28_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB28_2:
+; RV32IFD-NEXT: beqz a0, .LBB28_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB28_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -2215,13 +2184,10 @@ define i32 @ustest_f64i32_mm(double %x) {
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft0, ft0
-; RV32IFD-NEXT: bnez a0, .LBB29_2
-; RV32IFD-NEXT: # %bb.1: # %entry
-; RV32IFD-NEXT: li a0, 0
-; RV32IFD-NEXT: addi sp, sp, 16
-; RV32IFD-NEXT: ret
-; RV32IFD-NEXT: .LBB29_2:
+; RV32IFD-NEXT: beqz a0, .LBB29_2
+; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
+; RV32IFD-NEXT: .LBB29_2: # %entry
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
@@ -2255,12 +2221,10 @@ define i32 @stest_f32i32_mm(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB30_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB30_2:
+; RV32-NEXT: beqz a0, .LBB30_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32-NEXT: .LBB30_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: stest_f32i32_mm:
@@ -2293,12 +2257,10 @@ define i32 @utest_f32i32_mm(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB31_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB31_2:
+; RV32-NEXT: beqz a0, .LBB31_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT: .LBB31_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: utest_f32i32_mm:
@@ -2324,12 +2286,10 @@ define i32 @ustest_f32i32_mm(float %x) {
; RV32: # %bb.0: # %entry
; RV32-NEXT: fmv.w.x ft0, a0
; RV32-NEXT: feq.s a0, ft0, ft0
-; RV32-NEXT: bnez a0, .LBB32_2
-; RV32-NEXT: # %bb.1: # %entry
-; RV32-NEXT: li a0, 0
-; RV32-NEXT: ret
-; RV32-NEXT: .LBB32_2:
+; RV32-NEXT: beqz a0, .LBB32_2
+; RV32-NEXT: # %bb.1:
; RV32-NEXT: fcvt.wu.s a0, ft0, rtz
+; RV32-NEXT: .LBB32_2: # %entry
; RV32-NEXT: ret
;
; RV64-LABEL: ustest_f32i32_mm:
@@ -3272,12 +3232,10 @@ define i64 @stest_f64i64_mm(double %x) {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
-; RV64IFD-NEXT: bnez a0, .LBB45_2
-; RV64IFD-NEXT: # %bb.1: # %entry
-; RV64IFD-NEXT: li a0, 0
-; RV64IFD-NEXT: ret
-; RV64IFD-NEXT: .LBB45_2:
+; RV64IFD-NEXT: beqz a0, .LBB45_2
+; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
+; RV64IFD-NEXT: .LBB45_2: # %entry
; RV64IFD-NEXT: ret
entry:
%conv = fptosi double %x to i128
@@ -3645,12 +3603,10 @@ define i64 @stest_f32i64_mm(float %x) {
; RV64: # %bb.0: # %entry
; RV64-NEXT: fmv.w.x ft0, a0
; RV64-NEXT: feq.s a0, ft0, ft0
-; RV64-NEXT: bnez a0, .LBB48_2
-; RV64-NEXT: # %bb.1: # %entry
-; RV64-NEXT: li a0, 0
-; RV64-NEXT: ret
-; RV64-NEXT: .LBB48_2:
+; RV64-NEXT: beqz a0, .LBB48_2
+; RV64-NEXT: # %bb.1:
; RV64-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64-NEXT: .LBB48_2: # %entry
; RV64-NEXT: ret
entry:
%conv = fptosi float %x to i128
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 84ab7162cec3..a862c9733d95 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -65,11 +65,8 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IZFH-NEXT: bnez a0, .LBB1_2
-; RV32IZFH-NEXT: # %bb.1: # %start
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB1_2:
+; RV32IZFH-NEXT: beqz a0, .LBB1_2
+; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI1_1)
@@ -77,17 +74,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: .LBB1_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_si_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IZFH-NEXT: bnez a0, .LBB1_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB1_2:
+; RV64IZFH-NEXT: beqz a0, .LBB1_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI1_1)
@@ -95,17 +90,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: .LBB1_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_si_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT: bnez a0, .LBB1_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: li a0, 0
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB1_2:
+; RV32IDZFH-NEXT: beqz a0, .LBB1_2
+; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
@@ -113,17 +106,15 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: .LBB1_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_si_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT: bnez a0, .LBB1_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB1_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB1_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI1_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI1_1)
@@ -131,6 +122,7 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: .LBB1_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_si_h_sat:
@@ -464,45 +456,37 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_w_h_sat:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB5_2
-; RV32IZFH-NEXT: # %bb.1: # %start
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB5_2:
+; RV32IZFH-NEXT: beqz a0, .LBB5_2
+; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT: .LBB5_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB5_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB5_2:
+; RV64IZFH-NEXT: beqz a0, .LBB5_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB5_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT: bnez a0, .LBB5_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: li a0, 0
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB5_2:
+; RV32IDZFH-NEXT: beqz a0, .LBB5_2
+; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IDZFH-NEXT: .LBB5_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_w_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT: bnez a0, .LBB5_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB5_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB5_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV64IDZFH-NEXT: .LBB5_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_w_h_sat:
@@ -746,45 +730,37 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV32IZFH-LABEL: fcvt_wu_h_sat:
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB8_2
-; RV32IZFH-NEXT: # %bb.1: # %start
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB8_2:
+; RV32IZFH-NEXT: beqz a0, .LBB8_2
+; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: .LBB8_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_wu_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB8_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB8_2:
+; RV64IZFH-NEXT: beqz a0, .LBB8_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB8_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_wu_h_sat:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IDZFH-NEXT: bnez a0, .LBB8_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: li a0, 0
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB8_2:
+; RV32IDZFH-NEXT: beqz a0, .LBB8_2
+; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: .LBB8_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_wu_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT: bnez a0, .LBB8_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB8_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB8_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV64IDZFH-NEXT: .LBB8_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_wu_h_sat:
@@ -984,12 +960,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64IZFH-LABEL: fcvt_l_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB10_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB10_2:
+; RV64IZFH-NEXT: beqz a0, .LBB10_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB10_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_l_h_sat:
@@ -1051,12 +1025,10 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64IDZFH-LABEL: fcvt_l_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT: bnez a0, .LBB10_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB10_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB10_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
+; RV64IDZFH-NEXT: .LBB10_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_l_h_sat:
@@ -1300,12 +1272,10 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64IZFH-LABEL: fcvt_lu_h_sat:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB12_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB12_2:
+; RV64IZFH-NEXT: beqz a0, .LBB12_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB12_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_lu_h_sat:
@@ -1354,12 +1324,10 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64IDZFH-LABEL: fcvt_lu_h_sat:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IDZFH-NEXT: bnez a0, .LBB12_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB12_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB12_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IDZFH-NEXT: .LBB12_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_lu_h_sat:
@@ -2425,11 +2393,8 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IZFH-NEXT: bnez a0, .LBB32_2
-; RV32IZFH-NEXT: # %bb.1: # %start
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB32_2:
+; RV32IZFH-NEXT: beqz a0, .LBB32_2
+; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI32_1)
@@ -2437,17 +2402,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: .LBB32_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IZFH-NEXT: bnez a0, .LBB32_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB32_2:
+; RV64IZFH-NEXT: beqz a0, .LBB32_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI32_1)
@@ -2455,17 +2418,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: .LBB32_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT: bnez a0, .LBB32_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: li a0, 0
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB32_2:
+; RV32IDZFH-NEXT: beqz a0, .LBB32_2
+; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
@@ -2473,17 +2434,15 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: .LBB32_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i16:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT: bnez a0, .LBB32_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB32_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB32_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI32_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI32_1)
@@ -2491,6 +2450,7 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: .LBB32_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i16:
@@ -2827,11 +2787,8 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32IZFH: # %bb.0: # %start
; RV32IZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IZFH-NEXT: bnez a0, .LBB36_2
-; RV32IZFH-NEXT: # %bb.1: # %start
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB36_2:
+; RV32IZFH-NEXT: beqz a0, .LBB36_2
+; RV32IZFH-NEXT: # %bb.1:
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV32IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
; RV32IZFH-NEXT: lui a0, %hi(.LCPI36_1)
@@ -2839,17 +2796,15 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IZFH-NEXT: .LBB36_2: # %start
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IZFH: # %bb.0: # %start
; RV64IZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IZFH-NEXT: bnez a0, .LBB36_2
-; RV64IZFH-NEXT: # %bb.1: # %start
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB36_2:
+; RV64IZFH-NEXT: beqz a0, .LBB36_2
+; RV64IZFH-NEXT: # %bb.1:
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV64IZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
; RV64IZFH-NEXT: lui a0, %hi(.LCPI36_1)
@@ -2857,17 +2812,15 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV64IZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IZFH-NEXT: .LBB36_2: # %start
; RV64IZFH-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV32IDZFH: # %bb.0: # %start
; RV32IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV32IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV32IDZFH-NEXT: bnez a0, .LBB36_2
-; RV32IDZFH-NEXT: # %bb.1: # %start
-; RV32IDZFH-NEXT: li a0, 0
-; RV32IDZFH-NEXT: ret
-; RV32IDZFH-NEXT: .LBB36_2:
+; RV32IDZFH-NEXT: beqz a0, .LBB36_2
+; RV32IDZFH-NEXT: # %bb.1:
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV32IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
; RV32IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
@@ -2875,17 +2828,15 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV32IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV32IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV32IDZFH-NEXT: fcvt.w.s a0, ft0, rtz
+; RV32IDZFH-NEXT: .LBB36_2: # %start
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_w_s_sat_i8:
; RV64IDZFH: # %bb.0: # %start
; RV64IDZFH-NEXT: fcvt.s.h ft0, fa0
; RV64IDZFH-NEXT: feq.s a0, ft0, ft0
-; RV64IDZFH-NEXT: bnez a0, .LBB36_2
-; RV64IDZFH-NEXT: # %bb.1: # %start
-; RV64IDZFH-NEXT: li a0, 0
-; RV64IDZFH-NEXT: ret
-; RV64IDZFH-NEXT: .LBB36_2:
+; RV64IDZFH-NEXT: beqz a0, .LBB36_2
+; RV64IDZFH-NEXT: # %bb.1:
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_0)
; RV64IDZFH-NEXT: flw ft1, %lo(.LCPI36_0)(a0)
; RV64IDZFH-NEXT: lui a0, %hi(.LCPI36_1)
@@ -2893,6 +2844,7 @@ define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
; RV64IDZFH-NEXT: fmax.s ft0, ft0, ft1
; RV64IDZFH-NEXT: fmin.s ft0, ft0, ft2
; RV64IDZFH-NEXT: fcvt.l.s a0, ft0, rtz
+; RV64IDZFH-NEXT: .LBB36_2: # %start
; RV64IDZFH-NEXT: ret
;
; RV32I-LABEL: fcvt_w_s_sat_i8:
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
index 7b3104c69bef..163c792d8a9e 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll
@@ -8,23 +8,19 @@ define signext i32 @test_floor_si32(half %x) {
; RV32IZFH-LABEL: test_floor_si32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB0_2
+; RV32IZFH-NEXT: beqz a0, .LBB0_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB0_2:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rdn
+; RV32IZFH-NEXT: .LBB0_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_si32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB0_2
+; RV64IZFH-NEXT: beqz a0, .LBB0_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB0_2:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rdn
+; RV64IZFH-NEXT: .LBB0_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
@@ -94,12 +90,10 @@ define i64 @test_floor_si64(half %x) nounwind {
; RV64IZFH-LABEL: test_floor_si64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB1_2
+; RV64IZFH-NEXT: beqz a0, .LBB1_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB1_2:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rdn
+; RV64IZFH-NEXT: .LBB1_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
@@ -110,23 +104,19 @@ define signext i32 @test_floor_ui32(half %x) {
; RV32IZFH-LABEL: test_floor_ui32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB2_2
+; RV32IZFH-NEXT: beqz a0, .LBB2_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB2_2:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; RV32IZFH-NEXT: .LBB2_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_floor_ui32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB2_2
+; RV64IZFH-NEXT: beqz a0, .LBB2_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB2_2:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rdn
+; RV64IZFH-NEXT: .LBB2_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -183,12 +173,10 @@ define i64 @test_floor_ui64(half %x) nounwind {
; RV64IZFH-LABEL: test_floor_ui64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB3_2
+; RV64IZFH-NEXT: beqz a0, .LBB3_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB3_2:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rdn
+; RV64IZFH-NEXT: .LBB3_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.floor.f16(half %x)
%b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
@@ -199,23 +187,19 @@ define signext i32 @test_ceil_si32(half %x) {
; RV32IZFH-LABEL: test_ceil_si32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB4_2
+; RV32IZFH-NEXT: beqz a0, .LBB4_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB4_2:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rup
+; RV32IZFH-NEXT: .LBB4_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_si32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB4_2
+; RV64IZFH-NEXT: beqz a0, .LBB4_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB4_2:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rup
+; RV64IZFH-NEXT: .LBB4_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
@@ -285,12 +269,10 @@ define i64 @test_ceil_si64(half %x) nounwind {
; RV64IZFH-LABEL: test_ceil_si64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB5_2
+; RV64IZFH-NEXT: beqz a0, .LBB5_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB5_2:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rup
+; RV64IZFH-NEXT: .LBB5_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
@@ -301,23 +283,19 @@ define signext i32 @test_ceil_ui32(half %x) {
; RV32IZFH-LABEL: test_ceil_ui32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB6_2
+; RV32IZFH-NEXT: beqz a0, .LBB6_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB6_2:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; RV32IZFH-NEXT: .LBB6_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_ceil_ui32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB6_2
+; RV64IZFH-NEXT: beqz a0, .LBB6_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB6_2:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rup
+; RV64IZFH-NEXT: .LBB6_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -374,12 +352,10 @@ define i64 @test_ceil_ui64(half %x) nounwind {
; RV64IZFH-LABEL: test_ceil_ui64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB7_2
+; RV64IZFH-NEXT: beqz a0, .LBB7_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB7_2:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rup
+; RV64IZFH-NEXT: .LBB7_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.ceil.f16(half %x)
%b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
@@ -390,23 +366,19 @@ define signext i32 @test_trunc_si32(half %x) {
; RV32IZFH-LABEL: test_trunc_si32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB8_2
+; RV32IZFH-NEXT: beqz a0, .LBB8_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB8_2:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV32IZFH-NEXT: .LBB8_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_si32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB8_2
+; RV64IZFH-NEXT: beqz a0, .LBB8_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB8_2:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB8_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
@@ -476,12 +448,10 @@ define i64 @test_trunc_si64(half %x) nounwind {
; RV64IZFH-LABEL: test_trunc_si64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB9_2
+; RV64IZFH-NEXT: beqz a0, .LBB9_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB9_2:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB9_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
@@ -492,23 +462,19 @@ define signext i32 @test_trunc_ui32(half %x) {
; RV32IZFH-LABEL: test_trunc_ui32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB10_2
+; RV32IZFH-NEXT: beqz a0, .LBB10_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB10_2:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: .LBB10_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_trunc_ui32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB10_2
+; RV64IZFH-NEXT: beqz a0, .LBB10_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB10_2:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB10_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -565,12 +531,10 @@ define i64 @test_trunc_ui64(half %x) nounwind {
; RV64IZFH-LABEL: test_trunc_ui64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB11_2
+; RV64IZFH-NEXT: beqz a0, .LBB11_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB11_2:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT: .LBB11_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.trunc.f16(half %x)
%b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
@@ -581,23 +545,19 @@ define signext i32 @test_round_si32(half %x) {
; RV32IZFH-LABEL: test_round_si32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB12_2
+; RV32IZFH-NEXT: beqz a0, .LBB12_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB12_2:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
+; RV32IZFH-NEXT: .LBB12_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_si32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB12_2
+; RV64IZFH-NEXT: beqz a0, .LBB12_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB12_2:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm
+; RV64IZFH-NEXT: .LBB12_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
@@ -667,12 +627,10 @@ define i64 @test_round_si64(half %x) nounwind {
; RV64IZFH-LABEL: test_round_si64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB13_2
+; RV64IZFH-NEXT: beqz a0, .LBB13_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB13_2:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
+; RV64IZFH-NEXT: .LBB13_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
@@ -683,23 +641,19 @@ define signext i32 @test_round_ui32(half %x) {
; RV32IZFH-LABEL: test_round_ui32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB14_2
+; RV32IZFH-NEXT: beqz a0, .LBB14_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB14_2:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; RV32IZFH-NEXT: .LBB14_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_round_ui32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB14_2
+; RV64IZFH-NEXT: beqz a0, .LBB14_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB14_2:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rmm
+; RV64IZFH-NEXT: .LBB14_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -756,12 +710,10 @@ define i64 @test_round_ui64(half %x) nounwind {
; RV64IZFH-LABEL: test_round_ui64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB15_2
+; RV64IZFH-NEXT: beqz a0, .LBB15_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB15_2:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rmm
+; RV64IZFH-NEXT: .LBB15_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.round.f16(half %x)
%b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
@@ -772,23 +724,19 @@ define signext i32 @test_roundeven_si32(half %x) {
; RV32IZFH-LABEL: test_roundeven_si32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB16_2
+; RV32IZFH-NEXT: beqz a0, .LBB16_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB16_2:
; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rne
+; RV32IZFH-NEXT: .LBB16_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_si32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB16_2
+; RV64IZFH-NEXT: beqz a0, .LBB16_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB16_2:
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rne
+; RV64IZFH-NEXT: .LBB16_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
@@ -858,12 +806,10 @@ define i64 @test_roundeven_si64(half %x) nounwind {
; RV64IZFH-LABEL: test_roundeven_si64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB17_2
+; RV64IZFH-NEXT: beqz a0, .LBB17_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB17_2:
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rne
+; RV64IZFH-NEXT: .LBB17_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
@@ -874,23 +820,19 @@ define signext i32 @test_roundeven_ui32(half %x) {
; RV32IZFH-LABEL: test_roundeven_ui32:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: feq.h a0, fa0, fa0
-; RV32IZFH-NEXT: bnez a0, .LBB18_2
+; RV32IZFH-NEXT: beqz a0, .LBB18_2
; RV32IZFH-NEXT: # %bb.1:
-; RV32IZFH-NEXT: li a0, 0
-; RV32IZFH-NEXT: ret
-; RV32IZFH-NEXT: .LBB18_2:
; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; RV32IZFH-NEXT: .LBB18_2:
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: test_roundeven_ui32:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB18_2
+; RV64IZFH-NEXT: beqz a0, .LBB18_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB18_2:
; RV64IZFH-NEXT: fcvt.wu.h a0, fa0, rne
+; RV64IZFH-NEXT: .LBB18_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
@@ -947,12 +889,10 @@ define i64 @test_roundeven_ui64(half %x) nounwind {
; RV64IZFH-LABEL: test_roundeven_ui64:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: feq.h a0, fa0, fa0
-; RV64IZFH-NEXT: bnez a0, .LBB19_2
+; RV64IZFH-NEXT: beqz a0, .LBB19_2
; RV64IZFH-NEXT: # %bb.1:
-; RV64IZFH-NEXT: li a0, 0
-; RV64IZFH-NEXT: ret
-; RV64IZFH-NEXT: .LBB19_2:
; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rne
+; RV64IZFH-NEXT: .LBB19_2:
; RV64IZFH-NEXT: ret
%a = call half @llvm.roundeven.f16(half %x)
%b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
diff --git a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
index 28e9d1c7bc40..4b5f18de7d17 100644
--- a/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
+++ b/llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll
@@ -16,12 +16,10 @@ define dso_local i32 @test_zext_i8() nounwind {
; RV32I-NEXT: xori a1, a1, 136
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: bnez a0, .LBB0_2
-; RV32I-NEXT: # %bb.1: # %if.end
-; RV32I-NEXT: li a0, 0
-; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB0_2: # %if.then
+; RV32I-NEXT: beqz a0, .LBB0_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: .LBB0_2: # %if.end
; RV32I-NEXT: ret
entry:
%0 = load i8, i8* getelementptr inbounds ([5 x i8], [5 x i8]* @bytes, i32 0, i32 0), align 1
@@ -52,12 +50,10 @@ define dso_local i32 @test_zext_i16() nounwind {
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: xori a0, a0, 7
; RV32I-NEXT: or a0, a1, a0
-; RV32I-NEXT: bnez a0, .LBB1_2
-; RV32I-NEXT: # %bb.1: # %if.end
-; RV32I-NEXT: li a0, 0
-; RV32I-NEXT: ret
-; RV32I-NEXT: .LBB1_2: # %if.then
+; RV32I-NEXT: beqz a0, .LBB1_2
+; RV32I-NEXT: # %bb.1: # %if.then
; RV32I-NEXT: li a0, 1
+; RV32I-NEXT: .LBB1_2: # %if.end
; RV32I-NEXT: ret
entry:
%0 = load i16, i16* getelementptr inbounds ([5 x i16], [5 x i16]* @shorts, i32 0, i32 0), align 2
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