[PATCH] D118305: [Spill2Reg] Added code generation support for 8/16bit spills/reloads in x86

[Vasileios Porpodas via Phabricator via llvm-commits]

vporpo updated this revision to Diff 405150.
vporpo added a comment.

Removed the subregs from the movd instructions.
Also added simple mir tests for 8/16 bits.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118305/new/

https://reviews.llvm.org/D118305

Files:
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.h
  llvm/test/CodeGen/X86/spill2reg_end_to_end_16bit.ll
  llvm/test/CodeGen/X86/spill2reg_end_to_end_8bit.ll
  llvm/test/CodeGen/X86/spill2reg_simple_1_16bit.mir
  llvm/test/CodeGen/X86/spill2reg_simple_1_8bit.mir

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