[llvm] 7f6441f - [TableGen][RISCV] Relax a restriction in generating patterns for commutable SDNodes.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 1 21:22:42 PST 2022
Author: Craig Topper
Date: 2022-02-01T21:07:03-08:00
New Revision: 7f6441f96e12798ed63290fff436f347f6aca3aa
URL: https://github.com/llvm/llvm-project/commit/7f6441f96e12798ed63290fff436f347f6aca3aa
DIFF: https://github.com/llvm/llvm-project/commit/7f6441f96e12798ed63290fff436f347f6aca3aa.diff
LOG: [TableGen][RISCV] Relax a restriction in generating patterns for commutable SDNodes.
Previously, all children would be checked to see if any were an
explicit Register. If anywhere no commutable patterns would be
generated. This patch loosens the restriction to only check the
children that are being commuted.
Digging back through history, this code predates the existence of
commutable intrinsics and commutable SDNodes with more than 2
operands. At that time the loop would count the number of children that
weren't registers and if that was equal to 2 it would allow commuting.
I don't think this loop was re-considered when commutable
intrinsics were added or when we allowed SDNodes with more than 2
operands.
This important for RISCV were our isel patterns have a V0 mask
operand after the commutable operands on some RISCVISD opcodes.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D117955
Added:
Modified:
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
llvm/utils/TableGen/CodeGenDAGPatterns.cpp
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
index 04365bdf0b9a7..19f46b98cf806 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
@@ -131,10 +131,8 @@ define <4 x i8> @vadd_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl
define <4 x i8> @vadd_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vx_v4i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
index d8d9e1745e12d..ae6bc5ac35b0f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
@@ -55,10 +55,8 @@ define <2 x i8> @vand_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl
define <2 x i8> @vand_vx_v2i8_commute(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vand_vx_v2i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vand.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
index 9f0fce0f60ea1..c585efbfa93d2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfadd-vp.ll
@@ -255,10 +255,8 @@ define <2 x float> @vfadd_vf_v2f32(<2 x float> %va, float %b, <2 x i1> %m, i32 z
define <2 x float> @vfadd_vf_v2f32_commute(<2 x float> %va, float %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfadd_vf_v2f32_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, mu
-; CHECK-NEXT: vfmv.v.f v9, fa0
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu
-; CHECK-NEXT: vfadd.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vfadd.vf v8, v8, fa0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x float> poison, float %b, i32 0
%vb = shufflevector <2 x float> %elt.head, <2 x float> poison, <2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
index a3c3fcb9f1854..4bfc4f43e06a8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll
@@ -355,10 +355,8 @@ define <8 x i16> @vmul_vx_v8i16(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext
define <8 x i16> @vmul_vx_v8i16_commute(<8 x i16> %va, i16 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmul_vx_v8i16_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
-; CHECK-NEXT: vmul.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i16> poison, i16 %b, i32 0
%vb = shufflevector <8 x i16> %elt.head, <8 x i16> poison, <8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
index 465df370f7de5..68cf1109d8396 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll
@@ -131,10 +131,8 @@ define <4 x i8> @vor_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl)
define <4 x i8> @vor_vx_v4i8_commute(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vor_vx_v4i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> poison, i8 %b, i32 0
%vb = shufflevector <4 x i8> %elt.head, <4 x i8> poison, <4 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
index 0c774b884f0a5..99a5e3883183c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
@@ -55,10 +55,8 @@ define <2 x i8> @vxor_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl
define <2 x i8> @vxor_vx_v2i8_commute(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vx_v2i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vxor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vxor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> poison, i8 %b, i32 0
%vb = shufflevector <2 x i8> %elt.head, <2 x i8> poison, <2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
index 0af3e7084c7c1..42819bebe43de 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll
@@ -57,10 +57,8 @@ define <vscale x 1 x i8> @vadd_vx_nxv1i8(<vscale x 1 x i8> %va, i8 %b, <vscale x
define <vscale x 1 x i8> @vadd_vx_nxv1i8_commute(<vscale x 1 x i8> %va, i8 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vadd_vx_nxv1i8_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
-; CHECK-NEXT: vadd.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vadd.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
index 85a1d7acd1418..fceb7e1b2387e 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-vp.ll
@@ -1045,10 +1045,8 @@ define <vscale x 32 x i16> @vand_vx_nxv32i16(<vscale x 32 x i16> %va, i16 %b, <v
define <vscale x 32 x i16> @vand_vx_nxv32i16_commute(<vscale x 32 x i16> %va, i16 %b, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vand_vx_nxv32i16_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e16, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
-; CHECK-NEXT: vand.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vand.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
index 3e53732ae687a..127db172ee951 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll
@@ -957,10 +957,8 @@ define <vscale x 16 x i32> @vmul_vx_nxv16i32(<vscale x 16 x i32> %va, i32 %b, <v
define <vscale x 16 x i32> @vmul_vx_nxv16i32_commute(<vscale x 16 x i32> %va, i32 %b, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vmul_vx_nxv16i32_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e32, m8, ta, mu
-; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
-; CHECK-NEXT: vmul.vv v8, v16, v8, v0.t
+; CHECK-NEXT: vmul.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
index bf067e63d4899..66d4c8c2d7954 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-vp.ll
@@ -1121,10 +1121,8 @@ define <vscale x 2 x i32> @vor_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscal
define <vscale x 2 x i32> @vor_vx_nxv2i32_commute(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vor_vx_nxv2i32_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e32, m1, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
-; CHECK-NEXT: vor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
index 8994310f91209..2fd2c8aaaf3d7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
@@ -873,10 +873,8 @@ define <vscale x 1 x i16> @vxor_vx_nxv1i16(<vscale x 1 x i16> %va, i16 %b, <vsca
define <vscale x 1 x i16> @vxor_vx_nxv1i16_commute(<vscale x 1 x i16> %va, i16 %b, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vxor_vx_nxv1i16_commute:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli a2, zero, e16, mf4, ta, mu
-; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
-; CHECK-NEXT: vxor.vv v8, v9, v8, v0.t
+; CHECK-NEXT: vxor.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
diff --git a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
index 4de619df5b5f6..a1f8f4809d5f9 100644
--- a/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -4645,39 +4645,33 @@ static void GenerateVariantsOf(TreePatternNodePtr N,
// If this node is commutative, consider the commuted order.
bool isCommIntrinsic = N->isCommutativeIntrinsic(CDP);
if (NodeInfo.hasProperty(SDNPCommutative) || isCommIntrinsic) {
- assert((N->getNumChildren()>=2 || isCommIntrinsic) &&
+ unsigned Skip = isCommIntrinsic ? 1 : 0; // First operand is intrinsic id.
+ assert(N->getNumChildren() >= (2 + Skip) &&
"Commutative but doesn't have 2 children!");
- // Don't count children which are actually register references.
- unsigned NC = 0;
- for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) {
+ // Don't allow commuting children which are actually register references.
+ bool NoRegisters = true;
+ unsigned i = 0 + Skip;
+ unsigned e = 2 + Skip;
+ for (; i != e; ++i) {
TreePatternNode *Child = N->getChild(i);
if (Child->isLeaf())
if (DefInit *DI = dyn_cast<DefInit>(Child->getLeafValue())) {
Record *RR = DI->getDef();
if (RR->isSubClassOf("Register"))
- continue;
+ NoRegisters = false;
}
- NC++;
}
// Consider the commuted order.
- if (isCommIntrinsic) {
- // Commutative intrinsic. First operand is the intrinsic id, 2nd and 3rd
- // operands are the commutative operands, and there might be more operands
- // after those.
- assert(NC >= 3 &&
- "Commutative intrinsic should have at least 3 children!");
- std::vector<std::vector<TreePatternNodePtr>> Variants;
- Variants.push_back(std::move(ChildVariants[0])); // Intrinsic id.
- Variants.push_back(std::move(ChildVariants[2]));
- Variants.push_back(std::move(ChildVariants[1]));
- for (unsigned i = 3; i != NC; ++i)
- Variants.push_back(std::move(ChildVariants[i]));
- CombineChildVariants(N, Variants, OutVariants, CDP, DepVars);
- } else if (NC == N->getNumChildren()) {
+ if (NoRegisters) {
std::vector<std::vector<TreePatternNodePtr>> Variants;
- Variants.push_back(std::move(ChildVariants[1]));
- Variants.push_back(std::move(ChildVariants[0]));
- for (unsigned i = 2; i != NC; ++i)
+ unsigned i = 0;
+ if (isCommIntrinsic)
+ Variants.push_back(std::move(ChildVariants[i++])); // Intrinsic id.
+ Variants.push_back(std::move(ChildVariants[i + 1]));
+ Variants.push_back(std::move(ChildVariants[i]));
+ i += 2;
+ // Remaining operands are not commuted.
+ for (; i != N->getNumChildren(); ++i)
Variants.push_back(std::move(ChildVariants[i]));
CombineChildVariants(N, Variants, OutVariants, CDP, DepVars);
}
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