[PATCH] D110579: [AMDGPU] Add a new intrinsic to control fp_trunc rounding mode

[Jay Foad via Phabricator via llvm-commits]

foad added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3252
     return selectG_SBFX_UBFX(I);
+  case AMDGPU::G_FPTRUNC_ROUND_UPWARD:
+  case AMDGPU::G_FPTRUNC_ROUND_DOWNWARD: {
----------------
jpages wrote:
> foad wrote:
> > Can this be done with patterns in the tablegen files instead of C++ code?
> Maybe it's possible, but I could not find a way to match both the G_FPTRUNC_ROUND_UPWARD and the selection DAG version. 
> 
> So I let this one in C++.
You can get some clues about GlobalISel pattern problems by running tablegen with -warn-on-skipped-patterns like this:
```
$ llvm-tblgen -gen-global-isel -I lib/Target/AMDGPU -I build/include -I include -I lib/Target lib/Target/AMDGPU/AMDGPUGISel.td -warn-on-skipped-patterns
...
lib/Target/AMDGPU/SIInstructions.td:186:1: warning: Skipped pattern: Pattern operator lacks an equivalent Instruction (AMDGPUISD::FPTRUNC_ROUND_UPWARD)
def FPTRUNC_UPWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
^
...
lib/Target/AMDGPU/SIInstructions.td:190:1: warning: Skipped pattern: Pattern operator lacks an equivalent Instruction (AMDGPUISD::FPTRUNC_ROUND_DOWNWARD)
def FPTRUNC_DOWNWARD_PSEUDO : VPseudoInstSI <(outs VGPR_32:$vdst),
^
```
This means you need to add some `GINodeEquiv` lines in AMDGPUGISel.td.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:188
+  (ins i1imm:$imm1, VGPR_32:$src0, i1imm:$imm2, i1imm:$imm3),
+  [(set f32:$vdst, (SIfptrunc_round_upward i1:$imm1, f32:$src0, i1:$imm2, i1:$imm3))]> {}
+
----------------
Just end the line with `;` if there is nothing to go inside the `{}`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110579/new/

https://reviews.llvm.org/D110579