[PATCH] D110579: [AMDGPU] Add a new intrinsic to control fp_trunc rounding mode

[Julien Pagès via Phabricator via llvm-commits]

jpages marked 12 inline comments as done.
jpages added a comment.

Thanks again for all the comments!



================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:6377
+
+    if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
+      EVT VT = TLI.getValueType(DAG.getDataLayout(), PTy);
----------------
craig.topper wrote:
> I know this was taken from visitTargetIntrinsic, but I don't really understand it.
I removed this line, I'm not sure of what it was doing either.


================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3252
     return selectG_SBFX_UBFX(I);
+  case AMDGPU::G_FPTRUNC_ROUND_UPWARD:
+  case AMDGPU::G_FPTRUNC_ROUND_DOWNWARD: {
----------------
foad wrote:
> Can this be done with patterns in the tablegen files instead of C++ code?
Maybe it's possible, but I could not find a way to match both the G_FPTRUNC_ROUND_UPWARD and the selection DAG version. 

So I let this one in C++.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:182-183
+let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [MODE, EXEC] in {
+def FPTRUNC_UPWARD_PSEUDO : SPseudoInstSI <(outs unknown:$sdst), (ins unknown:$src0)>;
+def FPTRUNC_DOWNWARD_PSEUDO : SPseudoInstSI <(outs unknown:$sdst), (ins unknown:$src0)>;
+} // End let usesCustomInserter = 1, hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [MODE, EXEC]
----------------
foad wrote:
> Can you implement instruction selection for the intrinsics by adding patterns here, instead of writing C++ code?
Like I said previously, I tried to use pure tablegen for both SelectionDag and global-isel and I could not find a way to do it for both.




CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110579/new/

https://reviews.llvm.org/D110579