[PATCH] D118549: apply two more cases for store combine

[Baoshan Pang via Phabricator via llvm-commits]

BaoshanPang created this revision.
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1. handle the case with extra shift
2. use two short(16-bits) store for 4 byte store when one word store is not allowed


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118549

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/RISCV/store-combine.ll

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