[llvm] 815786e - [RISCV] Use RVBUnary to simplify ZEXT_H_RV32/ZEXT_H_RV64 definitions. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-01-29T18:28:14-08:00
New Revision: 815786eb67e89d1efe35b0ad6c143d5d7cc5577a

URL: https://github.com/llvm/llvm-project/commit/815786eb67e89d1efe35b0ad6c143d5d7cc5577a
DIFF: https://github.com/llvm/llvm-project/commit/815786eb67e89d1efe35b0ad6c143d5d7cc5577a.diff

LOG: [RISCV] Use RVBUnary to simplify ZEXT_H_RV32/ZEXT_H_RV64 definitions. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 1d74ca1acc77..702e13847694 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -588,21 +588,13 @@ def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
            Sched<[WriteBFP32, ReadBFP32, ReadBFP32]>;
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV32] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def ZEXT_H_RV32 : RVInstR<0b0000100, 0b100, OPC_OP, (outs GPR:$rd),
-                          (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
-                 Sched<[WriteIALU, ReadIALU]> {
-  let rs2 = 0b00000;
-}
+def ZEXT_H_RV32 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP, "zext.h">,
+                  Sched<[WriteIALU, ReadIALU]>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV32]
 
 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def ZEXT_H_RV64 : RVInstR<0b0000100, 0b100, OPC_OP_32, (outs GPR:$rd),
-                          (ins GPR:$rs1), "zext.h", "$rd, $rs1">,
-                 Sched<[WriteIALU, ReadIALU]> {
-  let rs2 = 0b00000;
-}
+def ZEXT_H_RV64 : RVBUnary<0b0000100, 0b00000, 0b100, OPC_OP_32, "zext.h">,
+                  Sched<[WriteIALU, ReadIALU]>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 // We treat rev8 and orc.b as standalone instructions even though they use a