[PATCH] D118461: [AMDGPU] Introduce new ISel combine for trunc-slr patterns

Fri Jan 28 08:05:45 PST 2022

foad added a comment.

In D118461#3279539 <https://reviews.llvm.org/D118461#3279539>, @tsymalla wrote:

> In D118461#3279351 <https://reviews.llvm.org/D118461#3279351>, @foad wrote:
>
>> It seems like the xor is getting in the way. Would something like D38161 <https://reviews.llvm.org/D38161> help instead?
>
> Currently, the xor gets combined to a setcc_ne which gets combined to the srl / trunc sequence.
> Initially, there is the xor / setcc_eq sequence which could be simplified like in D38161 <https://reviews.llvm.org/D38161>, removing the need for the xor.
> Probably that would clean up everything a bit.

Why do we even have the xor in the IR? Normally (if you run IR optimizations as well as backend passes) instcombine would combine it into the icmp. Why didn't this happen? Was it introduced late by StructurizeCFG? Does D118478 <https://reviews.llvm.org/D118478> help?

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https://reviews.llvm.org/D118461