[PATCH] D118461: [AMDGPU] Introduce new ISel combine for trunc-slr patterns

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Can this be done as a combine instead? Plus if we handle this for VALU, should also for SALU



================
Comment at: llvm/test/CodeGen/AMDGPU/dagcombine-lshr-and-cmp.ll:12
+  %2 = xor i1 %1, -1
+  br i1 %2, label %out.true, label %out.else
+
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Don't need control flow in this test. Also should test pattern for scalar and vector inputs


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  https://reviews.llvm.org/D118461/new/

https://reviews.llvm.org/D118461