[PATCH] D118305: [Spill2Reg] Added code generation support for 8/16bit spills/reloads in x86

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/X86/X86InstrInfo.cpp:9587
   case 32:
     return Insert ? X86::MOVDI2PDIrr : X86::MOVPDI2DIrr;
   case 64:
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Should use the AVX or AVX512 opcodes when available?

Are you limiting to VR128 regclass or do you allow VR128X with AVX512?


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Comment at: llvm/test/CodeGen/X86/spill2reg_end_to_end_16bit.ll:70
 ; CHECK-NEXT:    .cfi_offset %rbp, -16
-; CHECK-NEXT:    movzwl D0(%rip), %eax
-; CHECK-NEXT:    movw %ax, {{[-0-9]+}}(%r{{[sb]}}p) # 2-byte Spill
+; CHECK-NEXT:    movw D0(%rip), %ax
+; CHECK-NEXT:    movd %eax, %xmm3
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Why is X86FixupBWInsts.cpp failing to convert this load to movzwl?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118305/new/

https://reviews.llvm.org/D118305