[PATCH] D118368: [AMDGPU] SILoadStoreOptimizer: reject AGPR DS_WRITE sooner
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 27 10:24:03 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4b133cee8026: [AMDGPU] SILoadStoreOptimizer: reject AGPR DS_WRITE sooner (authored by foad).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118368/new/
https://reviews.llvm.org/D118368
Files:
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
Index: llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -974,15 +974,6 @@
continue;
if (&*MBBI == &*Paired.I) {
- // FIXME: nothing is illegal in a ds_write2 opcode with two AGPR data
- // operands. However we are reporting that ds_write2 shall have
- // only VGPR data so that machine copy propagation does not
- // create an illegal instruction with a VGPR and AGPR sources.
- // Consequenctially if we create such instruction the verifier
- // will complain.
- if (CI.IsAGPR && CI.InstClass == DS_WRITE)
- return false;
-
// We need to go through the list of instructions that we plan to
// move and make sure they are all safe to move down past the merged
// instruction.
@@ -2013,6 +2004,16 @@
if (!CI.hasMergeableAddress(*MRI))
continue;
+ if (CI.InstClass == DS_WRITE && CI.IsAGPR) {
+ // FIXME: nothing is illegal in a ds_write2 opcode with two AGPR data
+ // operands. However we are reporting that ds_write2 shall have
+ // only VGPR data so that machine copy propagation does not
+ // create an illegal instruction with a VGPR and AGPR sources.
+ // Consequenctially if we create such instruction the verifier
+ // will complain.
+ continue;
+ }
+
LLVM_DEBUG(dbgs() << "Mergeable: " << MI);
addInstToMergeableList(CI, MergeableInsts);
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