[PATCH] D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D117954#3276779 <https://reviews.llvm.org/D117954#3276779>, @craig.topper wrote:

> In D117954#3275106 <https://reviews.llvm.org/D117954#3275106>, @rogfer01 wrote:
>
>> Just to confirm, this is not fixed vector specific, is it?
>>
>> If this is the case could you add some tests for those?
>
> I think we only use ADD_VL and SUB_VL for fixed vectors, and VP intrinsics today. And we use VZEXT_VL and VSEXT_VL for fixed and scalable vectors, but we don't have VP intrinsics for them yet.
>
> So I think this code is fixed vector restricted right now because only fixed vectors use both ADD_VL/SUB_VL and VZEXT_VL/VSEXT_VL. Does that sound right, @frasercrmck ?

Yeah that sounds about right. I've been wondering if we should try and unify it all but I fear custom lowering `add` and co. would prohibit too many optimizations.


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https://reviews.llvm.org/D117954