[PATCH] D117954: [RISCV] Add DAG combines to transform ADD_VL/SUB_VL into widening add/sub.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 403712.
craig.topper added a comment.

Fix copy/paste comment mistake


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117954/new/

https://reviews.llvm.org/D117954

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwaddu.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsubu.ll

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