[PATCH] D118336: [RISCV] Avoid pointer element type access for masked atomicrmw intrinsics

[Alex Bradbury via Phabricator via llvm-commits]

asb added a comment.

I think it's always correct as well. The minimum width for atomic memory operations on RISC-V is 32-bits, but of course to do operations on smaller types you can use lr.w/sc.w and manipulate the loaded value or sometimes use one of the amo* operations with appropriately modified parameters for an equivalent result.


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  https://reviews.llvm.org/D118336/new/

https://reviews.llvm.org/D118336