[PATCH] D118336: [RISCV] Avoid pointer element type access for masked atomicrmw intrinsics

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I believe this is true; the "real" width is dealt with as part of the mask argument to the intrinsic, and as part of the IR expansion the input value for the RMW is shifted to the right position in the aligned i32. Looking at an i16 fetch+add the intrinsic gets an i32*.


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https://reviews.llvm.org/D118336