[PATCH] D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3
Djordje Todorovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 27 01:11:44 PST 2022
djtodoro added a comment.
In D113291#3274616 <https://reviews.llvm.org/D113291#3274616>, @gsocshubham wrote:
> Hello,
>
> I have a small query regarding this patch. The patch emits following llvm assembly for ctz table -
>
> -----Patch assembly-------
> // %bb.0:
>
> rbit w8, w0
> cmp w0, #0
> clz w8, w8
> csel w0, wzr, w8, eq
> ret
>
> ----------------------------------
>
> but in gcc, we have the following assembly being emitted -
>
> ------------GCC---------------------
> f(unsigned int):
>
> rbit w0, w0
> clz w0, w0
> and w0, w0, 31
> ret
>
> ------------------------------------------
>
> Reference - https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90838
>
> [1] My question is - To solve the bug, do I have to generate assembly similar to GCC?
>
> Please give me suggestions on moving forward in solving this bug.
Hi,
Is this really a bug?
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https://reviews.llvm.org/D113291/new/
https://reviews.llvm.org/D113291
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