[PATCH] D113291: [AggressiveInstCombine] Lower Table Based CTTZ and enable it for AARCH64 in -O3

Wed Jan 26 20:55:34 PST 2022

gsocshubham added a comment.

Hello,

I have a small query regarding this patch. The patch emits following llvm assembly for ctz table -

-----Patch assembly-------
// %bb.0:

  rbit w8, w0
  cmp w0, #0
  clz w8, w8
  csel w0, wzr, w8, eq
  ret

----------------------------------

but in gcc, we have the following assembly being emitted -

------------GCC---------------------
f(unsigned int):

  rbit    w0, w0
  clz     w0, w0
  and     w0, w0, 31
  ret

------------------------------------------

Reference - https://gcc.gnu.org/bugzilla/show_bug.cgi?id=90838

[1] My question is - To solve the bug, do I have to generate assembly similar to GCC?

Please give me suggestions on moving forward in solving this bug.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D113291/new/

https://reviews.llvm.org/D113291