[llvm] 6a4d3f3 - [RISCV] fix dead code

[Wu Xinlong via llvm-commits]

Author: Wu Xinlong
Date: 2022-01-27T16:00:01+08:00
New Revision: 6a4d3f37b5a7e8d74ce9279cc1437121730e2925

URL: https://github.com/llvm/llvm-project/commit/6a4d3f37b5a7e8d74ce9279cc1437121730e2925
DIFF: https://github.com/llvm/llvm-project/commit/6a4d3f37b5a7e8d74ce9279cc1437121730e2925.diff

LOG: [RISCV] fix dead code

fix dead code mentioned on https://reviews.llvm.org/D98136

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D118323

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
index 72d91b1044d65..01c6bd90ea587 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -191,8 +191,8 @@ enum OperandType : unsigned {
   OPERAND_SIMM12,
   OPERAND_UIMM20,
   OPERAND_UIMMLOG2XLEN,
-  OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN,
   OPERAND_RVKRNUM,
+  OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
   // Operand is either a register or uimm5, this is used by V extension pseudo
   // instructions to represent a value that be passed as AVL to either vsetvli
   // or vsetivli.