[llvm] 4ad517e - [CSKY] Add floating operation support including float and double
Zi Xuan Wu via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 26 23:55:23 PST 2022
Author: Zi Xuan Wu
Date: 2022-01-27T15:54:04+08:00
New Revision: 4ad517e6b0902ced1aeb179cabc9129a2007eca4
URL: https://github.com/llvm/llvm-project/commit/4ad517e6b0902ced1aeb179cabc9129a2007eca4
DIFF: https://github.com/llvm/llvm-project/commit/4ad517e6b0902ced1aeb179cabc9129a2007eca4.diff
LOG: [CSKY] Add floating operation support including float and double
CSKY arch has multiple FPU instruction versions such as FPU, FPUv2 and FPUv3 to implement floating operations.
For now, we just only support FPUv2 and FPUv3.
It includes the encoding, asm parsing of instructions and codegen of DAG nodes.
Added:
llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
llvm/test/CodeGen/CSKY/fpu/base-d.ll
llvm/test/CodeGen/CSKY/fpu/base-f.ll
llvm/test/CodeGen/CSKY/fpu/br-d.ll
llvm/test/CodeGen/CSKY/fpu/br-f.ll
llvm/test/CodeGen/CSKY/fpu/cmp-d.ll
llvm/test/CodeGen/CSKY/fpu/cmp-f.ll
llvm/test/CodeGen/CSKY/fpu/cvt-d.ll
llvm/test/CodeGen/CSKY/fpu/cvt-f.ll
llvm/test/CodeGen/CSKY/fpu/ldst-d.ll
llvm/test/CodeGen/CSKY/fpu/ldst-f.ll
llvm/test/CodeGen/CSKY/fpu/lit.local.cfg
llvm/test/MC/CSKY/fpuv2.s
llvm/test/MC/CSKY/fpuv3.s
Modified:
llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
llvm/lib/Target/CSKY/CSKY.td
llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
llvm/lib/Target/CSKY/CSKYISelLowering.cpp
llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
llvm/lib/Target/CSKY/CSKYInstrInfo.h
llvm/lib/Target/CSKY/CSKYInstrInfo.td
llvm/lib/Target/CSKY/CSKYRegisterInfo.td
llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h
llvm/test/CodeGen/CSKY/br.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
index 29b99a84a6cd3..a62bd111cba95 100644
--- a/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
+++ b/llvm/lib/Target/CSKY/AsmParser/CSKYAsmParser.cpp
@@ -303,6 +303,14 @@ struct CSKYOperand : public MCParsedAsmOperand {
bool isRegSeq() const { return isRegSeqTemplate<CSKY::R0, CSKY::R31>(); }
+ bool isRegSeqV1() const {
+ return isRegSeqTemplate<CSKY::F0_32, CSKY::F15_32>();
+ }
+
+ bool isRegSeqV2() const {
+ return isRegSeqTemplate<CSKY::F0_32, CSKY::F31_32>();
+ }
+
static bool isLegalRegList(unsigned from, unsigned to) {
if (from == 0 && to == 0)
return true;
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
index e26781ca6aa1d..ddb7fe93706eb 100644
--- a/llvm/lib/Target/CSKY/CSKY.td
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -11,6 +11,40 @@ include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// CSKY subtarget features and instruction predicates.
//===----------------------------------------------------------------------===//
+def ModeHardFloat :
+ SubtargetFeature<"hard-float", "UseHardFloat",
+ "true", "Use hard floating point features">;
+def ModeHardFloatABI :
+ SubtargetFeature<"hard-float-abi", "UseHardFloatABI",
+ "true", "Use hard floating point ABI to pass args">;
+
+def FeatureFPUV2_SF
+ : SubtargetFeature<"fpuv2_sf", "HasFPUv2SingleFloat", "true",
+ "Enable FPUv2 single float instructions">;
+def HasFPUv2_SF : Predicate<"Subtarget->hasFPUv2SingleFloat()">,
+ AssemblerPredicate<(all_of FeatureFPUV2_SF),
+ "Enable FPUv2 single float instructions">;
+
+def FeatureFPUV2_DF
+ : SubtargetFeature<"fpuv2_df", "HasFPUv2DoubleFloat", "true",
+ "Enable FPUv2 double float instructions">;
+def HasFPUv2_DF : Predicate<"Subtarget->hasFPUv2DoubleFloat()">,
+ AssemblerPredicate<(all_of FeatureFPUV2_DF),
+ "Enable FPUv2 double float instructions">;
+
+def FeatureFPUV3_SF
+ : SubtargetFeature<"fpuv3_sf", "HasFPUv3SingleFloat", "true",
+ "Enable FPUv3 single float instructions">;
+def HasFPUv3_SF : Predicate<"Subtarget->hasFPUv3SingleFloat()">,
+ AssemblerPredicate<(all_of FeatureFPUV3_SF),
+ "Enable FPUv3 single float instructions">;
+
+def FeatureFPUV3_DF
+ : SubtargetFeature<"fpuv3_df", "HasFPUv3DoubleFloat", "true",
+ "Enable FPUv3 double float instructions">;
+def HasFPUv3_DF : Predicate<"Subtarget->hasFPUv3DoubleFloat()">,
+ AssemblerPredicate<(all_of FeatureFPUV3_DF),
+ "Enable FPUv3 double float instructions">;
def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true",
"Use the 16-bit btsti instruction">;
diff --git a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
index 13e00deee5898..3ac335e2ad9d5 100644
--- a/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
+++ b/llvm/lib/Target/CSKY/CSKYConstantIslandPass.cpp
@@ -551,6 +551,11 @@ void CSKYConstantIslands::initializeFunctionInfo(
Bits = 16;
Scale = 4;
break;
+ case CSKY::f2FLRW_S:
+ case CSKY::f2FLRW_D:
+ Bits = 8;
+ Scale = 4;
+ break;
case CSKY::GRS32:
Bits = 17;
Scale = 2;
diff --git a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
index c4d5d687216d1..0b589e3d3e4f7 100644
--- a/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
+++ b/llvm/lib/Target/CSKY/CSKYISelLowering.cpp
@@ -38,6 +38,18 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
// Register Class
addRegisterClass(MVT::i32, &CSKY::GPRRegClass);
+ if (STI.useHardFloat()) {
+ if (STI.hasFPUv2SingleFloat())
+ addRegisterClass(MVT::f32, &CSKY::sFPR32RegClass);
+ else if (STI.hasFPUv3SingleFloat())
+ addRegisterClass(MVT::f32, &CSKY::FPR32RegClass);
+
+ if (STI.hasFPUv2DoubleFloat())
+ addRegisterClass(MVT::f64, &CSKY::sFPR64RegClass);
+ else if (STI.hasFPUv3DoubleFloat())
+ addRegisterClass(MVT::f64, &CSKY::FPR64RegClass);
+ }
+
setOperationAction(ISD::ADDCARRY, MVT::i32, Legal);
setOperationAction(ISD::SUBCARRY, MVT::i32, Legal);
setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
@@ -95,6 +107,40 @@ CSKYTargetLowering::CSKYTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
}
+ // Float
+
+ ISD::CondCode FPCCToExtend[] = {
+ ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
+ ISD::SETUGE, ISD::SETULT, ISD::SETULE,
+ };
+
+ ISD::NodeType FPOpToExpand[] = {ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
+ ISD::FPOW, ISD::FREM, ISD::FCOPYSIGN};
+
+ if (STI.useHardFloat()) {
+
+ MVT AllVTy[] = {MVT::f32, MVT::f64};
+
+ for (auto VT : AllVTy) {
+ setOperationAction(ISD::FREM, VT, Expand);
+ setOperationAction(ISD::SELECT_CC, VT, Expand);
+ setOperationAction(ISD::BR_CC, VT, Expand);
+
+ for (auto CC : FPCCToExtend)
+ setCondCodeAction(CC, VT, Expand);
+ for (auto Op : FPOpToExpand)
+ setOperationAction(Op, VT, Expand);
+ }
+
+ if (STI.hasFPUv2SingleFloat() || STI.hasFPUv3SingleFloat()) {
+ setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+ }
+ if (STI.hasFPUv2DoubleFloat() || STI.hasFPUv3DoubleFloat()) {
+ setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
+ setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+ }
+ }
+
// Compute derived properties from the register classes.
computeRegisterProperties(STI.getRegisterInfo());
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td b/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
new file mode 100644
index 0000000000000..446670a4d0a97
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormatsF1.td
@@ -0,0 +1,274 @@
+//===- CSKYInstrFormatsF1.td - CSKY Float1.0 Instr Format --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// CSKY Instruction Format Float1.0 Definitions.
+//
+//===----------------------------------------------------------------------===//
+
+class CSKYFP1Inst<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : CSKY32Inst<AddrModeNone, 0x3d, outs, ins, asmstr, pattern>, Requires<[HasFPUv2_SF]> {
+}
+
+class F_XYZ_BASE<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKYFP1Inst<outs, ins, opcodestr, pattern> {
+ bits<4> vrx;
+ bits<4> vry;
+ bits<4> vrz;
+ let Inst{25 - 21} = {0, vry};
+ let Inst{20 - 16} = {0, vrx};
+ let Inst{15 - 11} = datatype;
+ let Inst{10 - 5} = sop;
+ let Inst{4 - 0} = {0, vrz};
+}
+
+class F_XZ_GF<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKYFP1Inst<outs, ins, opcodestr, pattern> {
+ bits<4> vrx;
+ bits<5> rz;
+ let Inst{25 - 21} = 0;
+ let Inst{20 - 16} = {0, vrx};
+ let Inst{15 - 11} = datatype;
+ let Inst{10 - 5} = sop;
+ let Inst{4 - 0} = {rz};
+}
+
+class F_XZ_FG<bits<5> datatype, bits<6> sop, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKYFP1Inst<outs, ins, opcodestr, pattern> {
+ bits<5> rx;
+ bits<4> vrz;
+ let Inst{25 - 21} = 0;
+ let Inst{20 - 16} = {rx};
+ let Inst{15 - 11} = datatype;
+ let Inst{10 - 5} = sop;
+ let Inst{4 - 0} = {0, vrz};
+}
+
+class F_XZ_TRANS_FROM<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
+ : F_XZ_GF<3, sop, (outs regtype1:$rz), (ins regtype2:$vrx), !strconcat(op, "\t$rz, $vrx"),
+ []>;
+
+class F_XZ_TRANS_TO<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
+ : F_XZ_FG<3, sop, (outs regtype1:$vrz), (ins regtype2:$rx), !strconcat(op, "\t$vrz, $rx"),
+ []>;
+
+let vry = 0 in {
+class F_XZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
+ [(set regtype:$vrz, (opnode regtype:$vrx))]>;
+
+class F_MOV<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrz, $vrx"),
+ []>;
+
+class F_XZ_TRANS<bits<6> sop, string op, RegisterOperand regtype1, RegisterOperand regtype2>
+ : F_XYZ_BASE<3, sop, (outs regtype1:$vrz), (ins regtype2:$vrx), !strconcat(op, "\t$vrz, $vrx"),
+ []>;
+
+class F_XZ_TRANS_DS<bits<6> sop, string op, PatFrag opnode>
+ : F_XYZ_BASE<3, sop, (outs sFPR32Op:$vrz), (ins sFPR64Op:$vrx), !strconcat(op, "\t$vrz, $vrx"),
+ [(set sFPR32Op:$vrz, (opnode sFPR64Op:$vrx))]>;
+
+class F_XZ_TRANS_SD<bits<6> sop, string op, PatFrag opnode>
+ : F_XYZ_BASE<3, sop, (outs sFPR64Op:$vrz), (ins sFPR32Op:$vrx), !strconcat(op, "\t$vrz, $vrx"),
+ [(set sFPR64Op:$vrz, (opnode sFPR32Op:$vrx))]>;
+}
+
+multiclass FT_MOV<bits<6> sop, string op> {
+ def _S : F_MOV<0, sop, op, "s", sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_MOV<1, sop, op, "d", sFPR64Op>;
+}
+
+multiclass FT_XZ<bits<6> sop, string op, PatFrag opnode> {
+ def _S : F_XZ<0, sop, op, "s", opnode, sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XZ<1, sop, op, "d", opnode, sFPR64Op>;
+}
+
+let vrz = 0, isCompare = 1 in {
+class F_CMPXY<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry), !strconcat(op#op_su, "\t$vrx, $vry"),
+ []>;
+
+let vry = 0 in{
+class F_CMPZX<bits<5> datatype, bits<6> sop, string op, string op_su, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs CARRY:$ca), (ins regtype:$vrx), !strconcat(op#op_su, "\t$vrx"),
+ []>;
+}
+}
+
+class F_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrx, regtype:$vry),
+ !strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
+ [(set regtype:$vrz, (opnode regtype:$vrx, regtype:$vry))]>;
+
+multiclass FT_XYZ<bits<6> sop, string op, PatFrag opnode> {
+ def _S : F_XYZ<0, sop, op, "s", opnode, sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
+}
+
+let Constraints = "$vrt = $vrz" in {
+class F_ACCUM_XYZ<bits<5> datatype, bits<6> sop, string op, string op_su, PatFrag opnode, RegisterOperand regtype>
+ : F_XYZ_BASE<datatype, sop, (outs regtype:$vrz), (ins regtype:$vrt, regtype:$vrx, regtype:$vry),
+ !strconcat(op#op_su, "\t$vrz, $vrx, $vry"),
+ [(set regtype:$vrz, (opnode regtype:$vrt, regtype:$vrx, regtype:$vry))]>;
+}
+
+multiclass FT_ACCUM_XYZ<bits<6> sop, string op, PatFrag opnode> {
+ def _S : F_ACCUM_XYZ<0, sop, op, "s", opnode, sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_ACCUM_XYZ<1, sop, op, "d", opnode, sFPR64Op>;
+}
+
+multiclass FT_CMPXY<bits<6> sop, string op> {
+ def _S : F_CMPXY<0, sop, op, "s", sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_CMPXY<1, sop, op, "d", sFPR64Op>;
+}
+
+
+multiclass FT_CMPZX<bits<6> sop, string op> {
+ def _S : F_CMPZX<0, sop, op, "s", sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_CMPZX<1, sop, op, "d", sFPR64Op>;
+}
+
+class F_I8_XY_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKY32Inst<AddrMode32SDF, 0x3d, outs, ins, opcodestr, pattern> {
+ bits<5> rx;
+ bits<4> vrz;
+ bits<8> imm8;
+ let Inst{25} = 0;
+ let Inst{24 - 21} = imm8{7 - 4}; //imm4h
+ let Inst{20 - 16} = rx; //rx
+ let Inst{15 - 9} = sop;
+ let Inst{8} = sop_su;
+ let Inst{7 - 4} = imm8{3 - 0}; // imm4l
+ let Inst{3 - 0} = vrz;
+}
+
+class F_I4_XY_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKY32Inst<AddrMode32SDF, 0x3d, outs, ins, opcodestr, pattern> {
+ bits<10> regs;
+ bits<5> rx;
+
+ let Inst{25} = 0;
+ let Inst{24 - 21} = regs{3-0}; //imm4
+ let Inst{20 - 16} = rx; //rx
+ let Inst{15 - 9} = sop;
+ let Inst{8} = sop_su;
+ let Inst{7 - 4} = 0;
+ let Inst{3 - 0} = regs{8-5};
+}
+
+class F_I8_Z_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKY32Inst<AddrModeNone, 0x3d, outs, ins, opcodestr, pattern> {
+ bits<4> vrz;
+ bits<8> imm8;
+ let Inst{25} = 0;
+ let Inst{24 - 21} = imm8{7 - 4}; //imm4h
+ let Inst{20 - 16} = 0; //rx
+ let Inst{15 - 9} = sop;
+ let Inst{8} = sop_su;
+ let Inst{7 - 4} = imm8{3 - 0}; // imm4l
+ let Inst{3 - 0} = vrz;
+}
+
+class F_XYZ_MEM<bits<7> sop, bits<1> sop_su, dag outs, dag ins, string opcodestr, list<dag> pattern>
+ : CSKY32Inst<AddrModeNone, 0x3d, outs, ins, opcodestr, pattern> {
+ bits<5> rx;
+ bits<5> ry;
+ bits<4> vrz;
+ bits<2> imm;
+
+ let Inst{25 - 21} = ry; // ry;
+ let Inst{20 - 16} = rx; // rx;
+ let Inst{15 - 9} = sop;
+ let Inst{8} = sop_su;
+ let Inst{7} = 0;
+ let Inst{6,5} = imm; // shift;
+ let Inst{4} = 0;
+ let Inst{3 - 0} = vrz;
+}
+
+class F_XYAI_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
+ RegisterOperand regtype, Operand operand>
+ : F_I8_XY_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, operand:$imm8),
+ !strconcat(op#op_su, "\t$vrz, ($rx, ${imm8})"), []>;
+
+class F_XYAR_LD<bits<7> sop, bits<1> sop_su, string op, string op_su,
+ RegisterOperand regtype>
+ : F_XYZ_MEM<sop, sop_su, (outs regtype:$vrz), (ins GPR:$rx, GPR:$ry, uimm2:$imm),
+ op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>;
+
+class F_XYAI_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
+ RegisterOperand regtype, Operand operand>
+ : F_I8_XY_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, operand:$imm8),
+ !strconcat(op#op_su, "\t$vrz, ($rx, ${imm8})"), []>;
+
+class F_XYAR_ST<bits<7> sop, bits<1> sop_su, string op, string op_su,
+ RegisterOperand regtype>
+ : F_XYZ_MEM<sop, sop_su, (outs), (ins regtype:$vrz, GPR:$rx, GPR:$ry, uimm2:$imm),
+ op#op_su#"\t$vrz, ($rx, $ry << ${imm})", []>;
+
+def Mem8SL2 : Operand<iPTR>, ComplexPattern<iPTR, 2, "SelectAddrRegImm8", []> {
+ let MIOperandInfo = (ops GPR, i32imm);
+ let PrintMethod = "printAddrModeRegImmOperand";
+ let EncoderMethod = "getAddrModeFloatImm8_sl2OpValue";
+}
+
+def FRRS : Operand<iPTR>, ComplexPattern<iPTR, 3, "SelectAddrRegReg", []> {
+ let MIOperandInfo = (ops GPR, GPR, i32imm);
+ let PrintMethod = "printAddrModeRegRegSLOperand";
+ let EncoderMethod = "getAddrModeFloatRegRegSLOpValue";
+}
+
+multiclass FT_XYAI_LD<bits<7> sop, string op> {
+ def _S : F_XYAI_LD<sop, 0, op, "s", sFPR32Op, uimm8_2>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XYAI_LD<sop, 1, op, "d", sFPR64Op, uimm8_2>;
+}
+
+multiclass FT_XYAR_LD<bits<7> sop, string op> {
+ def _S : F_XYAR_LD<sop, 0, op, "s", sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XYAR_LD<sop, 1, op, "d", sFPR64Op>;
+}
+
+multiclass FT_XYAI_ST<bits<7> sop, string op> {
+ def _S : F_XYAI_ST<sop, 0, op, "s", sFPR32Op, uimm8_2>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XYAI_ST<sop, 1, op, "d", sFPR64Op, uimm8_2>;
+}
+
+multiclass FT_XYAR_ST<bits<7> sop, string op> {
+ def _S : F_XYAR_ST<sop, 0, op, "s", sFPR32Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_XYAR_ST<sop, 1, op, "d", sFPR64Op>;
+}
+
+multiclass FT_XYAR_STM<bits<7> sop, string op> {
+ def _S : F_I4_XY_MEM<sop, 0, (outs),
+ (ins GPR:$rx, regseq_f1:$regs, variable_ops),
+ !strconcat(op#"s", "\t$regs, (${rx})"), []>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_I4_XY_MEM<sop, 1, (outs),
+ (ins GPR:$rx, regseq_d1:$regs, variable_ops),
+ !strconcat(op#"d", "\t$regs, (${rx})"), []>;
+}
+
+multiclass FT_XYAR_LDM<bits<7> sop, string op> {
+ def _S : F_I4_XY_MEM<sop, 0, (outs),
+ (ins GPR:$rx, regseq_f1:$regs, variable_ops),
+ !strconcat(op#"s", "\t$regs, (${rx})"), []>;
+ let Predicates = [HasFPUv2_DF] in
+ def _D : F_I4_XY_MEM<sop, 1, (outs),
+ (ins GPR:$rx, regseq_d1:$regs, variable_ops),
+ !strconcat(op#"d", "\t$regs, (${rx})"), []>;
+}
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td b/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
new file mode 100644
index 0000000000000..641ad623f140e
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormatsF2.td
@@ -0,0 +1,208 @@
+//===- CSKYInstrFormatsF2.td - CSKY Float2.0 Instr Format --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// CSKY Instruction Format Float2.0 Definitions.
+//
+//===----------------------------------------------------------------------===//
+
+class CSKYInstF2<AddrMode am, dag outs, dag ins, string opcodestr,
+ list<dag> pattern>
+ : CSKY32Inst<am, 0x3d, outs, ins, opcodestr, pattern> {
+ let Predicates = [HasFPUv3_SF];
+ let DecoderNamespace = "FPUV3";
+}
+
+class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
+ list<dag> pattern>
+ : CSKYInstF2<AddrModeNone, outs, ins, opcodestr, pattern> {
+ bits<5> vry;
+ bits<5> vrx;
+ bits<5> vrz;
+
+ let Inst{25-21} = vry;
+ let Inst{20-16} = vrx;
+ let Inst{15-11} = datatype;
+ let Inst{10-5} = sop;
+ let Inst{4-0} = vrz;
+}
+
+multiclass F2_XYZ_T<bits<6> sop, string op, PatFrag opnode> {
+ def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
+ (outs FPR32Op:$vrz), (ins FPR32Op:$vrx, FPR32Op:$vry),
+ [(set FPR32Op:$vrz, (opnode FPR32Op:$vrx, FPR32Op:$vry))]>;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
+ (outs FPR64Op:$vrz), (ins FPR64Op:$vrx, FPR64Op:$vry),
+ [(set FPR64Op:$vrz, (opnode FPR64Op:$vrx, FPR64Op:$vry))]>;
+}
+
+let Constraints = "$vrZ = $vrz" in
+multiclass F2_XYZZ_T<bits<6> sop, string op, PatFrag opnode> {
+ def _S : F2_XYZ<0b00000, sop, op#".32"#"\t$vrz, $vrx, $vry",
+ (outs FPR32Op:$vrz), (ins FPR32Op:$vrZ, FPR32Op:$vrx, FPR32Op:$vry),
+ [(set FPR32Op:$vrz, (opnode FPR32Op:$vrx, FPR32Op:$vry, FPR32Op:$vrZ))]>;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_XYZ<0b00001, sop, op#".64"#"\t$vrz, $vrx, $vry",
+ (outs FPR64Op:$vrz), (ins FPR64Op:$vrZ, FPR64Op:$vrx, FPR64Op:$vry),
+ [(set FPR64Op:$vrz, (opnode FPR64Op:$vrx, FPR64Op:$vry, FPR64Op:$vrZ))]>;
+}
+
+let vry = 0 in {
+class F2_XZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op, SDNode opnode>
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx"),
+ (outs regtype:$vrz), (ins regtype:$vrx),
+ [(set regtype:$vrz, (opnode regtype:$vrx))]>;
+
+class F2_XZ_SET<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx"),
+ (outs regtype:$vrz), (ins regtype:$vrx),
+ []>;
+
+class F2_XZ_P<bits<5> datatype, bits<6> sop, string op, list<dag> pattern = [],
+ dag outs, dag ins>
+ : F2_XYZ<datatype, sop, op#"\t$vrz, $vrx", outs, ins, pattern>;
+}
+
+multiclass F2_XZ_RM<bits<5> datatype, bits<4> sop, string op, dag outs, dag ins> {
+ def _RN : F2_XZ_P<datatype, {sop, 0b00}, op#".rn", [], outs, ins>;
+ def _RZ : F2_XZ_P<datatype, {sop, 0b01}, op#".rz", [], outs, ins>;
+ def _RPI : F2_XZ_P<datatype, {sop, 0b10}, op#".rpi", [], outs, ins>;
+ def _RNI : F2_XZ_P<datatype, {sop, 0b11}, op#".rni", [], outs, ins>;
+}
+
+multiclass F2_XZ_T<bits<6> sop, string op, SDNode opnode> {
+ def _S : F2_XZ<0b00000, FPR32Op, sop, op#".32", opnode>;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_XZ<0b00001, FPR64Op, sop, op#".64", opnode>;
+}
+
+multiclass F2_XZ_SET_T<bits<6> sop, string op, string suffix = ""> {
+ def _S : F2_XZ_SET<0b00000, FPR32Op, sop, op#".32"#suffix>;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_XZ_SET<0b00001, FPR64Op, sop, op#".64"#suffix>;
+}
+
+
+let vrz = 0, isCompare = 1 in
+class F2_CXY<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx, $vry"),
+ (outs CARRY:$ca), (ins regtype:$vrx, regtype:$vry),
+ []>;
+
+multiclass F2_CXY_T<bits<6> sop, string op> {
+ def _S : F2_CXY<0b00000, FPR32Op, sop, op#".32">;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_CXY<0b00001, FPR64Op, sop, op#".64">;
+}
+
+
+let vrz = 0, vry = 0, isCompare = 1 in
+class F2_CX<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrx"),
+ (outs CARRY:$ca), (ins regtype:$vrx),
+ []>;
+
+multiclass F2_CX_T<bits<6> sop, string op> {
+ def _S : F2_CX<0b00000, FPR32Op, sop, op#".32">;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_CX<0b00001, FPR64Op, sop, op#".64">;
+}
+
+
+class F2_LDST<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
+ : CSKYInstF2<AddrMode32SDF, outs, ins,
+ !strconcat(op, "\t$vrz, ($rx, ${imm8})"), []> {
+ bits<10> imm8;
+ bits<5> rx;
+ bits<5> vrz;
+
+ let Inst{25} = vrz{4};
+ let Inst{24-21} = imm8{7-4};
+ let Inst{20-16} = rx;
+ let Inst{15-11} = 0b00100;
+ let Inst{10} = sop;
+ let Inst{9-8} = datatype;
+ let Inst{7-4} = imm8{3-0};
+ let Inst{3-0} = vrz{3-0};
+}
+
+class F2_LDST_S<bits<1> sop, string op, dag outs, dag ins>
+ : F2_LDST<0b00, sop, op#".32", outs, ins>;
+class F2_LDST_D<bits<1> sop, string op, dag outs, dag ins>
+ : F2_LDST<0b01, sop, op#".64", outs, ins>;
+
+class F2_LDSTM<bits<2> datatype, bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
+ : CSKYInstF2<AddrMode32SDF, outs, ins,
+ !strconcat(op, "\t$regs, (${rx})"), []> {
+ bits<10> regs;
+ bits<5> rx;
+
+ let Inst{25-21} = regs{4-0};
+ let Inst{20-16} = rx;
+ let Inst{15-11} = 0b00110;
+ let Inst{10} = sop;
+ let Inst{9-8} = datatype;
+ let Inst{7-5} = sop2;
+ let Inst{4-0} = regs{9-5};
+}
+
+class F2_LDSTM_S<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
+ : F2_LDSTM<0b00, sop, sop2, op#".32", outs, ins>;
+class F2_LDSTM_D<bits<1> sop, bits<3> sop2, string op, dag outs, dag ins>
+ : F2_LDSTM<0b01, sop, sop2, op#".64", outs, ins>;
+
+
+class F2_LDSTR<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
+ : CSKYInstF2<AddrModeNone, outs, ins,
+ op#"\t$rz, ($rx, $ry << ${imm})", []> {
+ bits<5> rx;
+ bits<5> ry;
+ bits<5> rz;
+ bits<2> imm;
+
+ let Inst{25-21} = ry;
+ let Inst{20-16} = rx;
+ let Inst{15-11} = 0b00101;
+ let Inst{10} = sop;
+ let Inst{9-8} = datatype;
+ let Inst{7} = 0;
+ let Inst{6-5} = imm;
+ let Inst{4-0} = rz;
+}
+
+class F2_LDSTR_S<bits<1> sop, string op, dag outs, dag ins>
+ : F2_LDSTR<0b00, sop, op#".32", outs, ins>;
+class F2_LDSTR_D<bits<1> sop, string op, dag outs, dag ins>
+ : F2_LDSTR<0b01, sop, op#".64", outs, ins>;
+
+class F2_CXYZ<bits<5> datatype, RegisterOperand regtype, bits<6> sop, string op>
+ : F2_XYZ<datatype, sop, !strconcat(op, "\t$vrz, $vrx, $vry"),
+ (outs regtype:$vrz), (ins CARRY:$ca, regtype:$vrx, regtype:$vry),
+ []>;
+multiclass F2_CXYZ_T<bits<6> sop, string op> {
+ def _S : F2_CXYZ<0b00000, FPR32Op, sop, op#".32">;
+ let Predicates = [HasFPUv3_DF] in
+ def _D : F2_CXYZ<0b00001, FPR64Op, sop, op#".64">;
+}
+
+class F2_LRW<bits<2> datatype, bits<1> sop, string op, dag outs, dag ins>
+ : CSKYInstF2<AddrModeNone, outs, ins,
+ !strconcat(op, "\t$vrz, ${imm8}"), []> {
+ bits<10> imm8;
+ bits<5> rx;
+ bits<5> vrz;
+
+ let Inst{25} = vrz{4};
+ let Inst{24-21} = imm8{7-4};
+ let Inst{20-16} = 0;
+ let Inst{15-11} = 0b00111;
+ let Inst{10} = sop;
+ let Inst{9-8} = datatype;
+ let Inst{7-4} = imm8{3-0};
+ let Inst{3-0} = vrz{3-0};
+}
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
index fce94c914f353..c57ccb9d6eea4 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
@@ -25,6 +25,10 @@ using namespace llvm;
CSKYInstrInfo::CSKYInstrInfo(CSKYSubtarget &STI)
: CSKYGenInstrInfo(CSKY::ADJCALLSTACKDOWN, CSKY::ADJCALLSTACKUP), STI(STI) {
+ v2sf = STI.hasFPUv2SingleFloat();
+ v2df = STI.hasFPUv2DoubleFloat();
+ v3sf = STI.hasFPUv3SingleFloat();
+ v3df = STI.hasFPUv3DoubleFloat();
}
static void parseCondBranch(MachineInstr &LastInst, MachineBasicBlock *&Target,
@@ -337,6 +341,10 @@ unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
case CSKY::LD32H:
case CSKY::LD32HS:
case CSKY::LD32W:
+ case CSKY::FLD_S:
+ case CSKY::FLD_D:
+ case CSKY::f2FLD_S:
+ case CSKY::f2FLD_D:
case CSKY::RESTORE_CARRY:
break;
}
@@ -361,6 +369,10 @@ unsigned CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
case CSKY::ST32B:
case CSKY::ST32H:
case CSKY::ST32W:
+ case CSKY::FST_S:
+ case CSKY::FST_D:
+ case CSKY::f2FST_S:
+ case CSKY::f2FST_D:
case CSKY::SPILL_CARRY:
break;
}
@@ -394,7 +406,15 @@ void CSKYInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
Opcode = CSKY::SPILL_CARRY;
CFI->setSpillsCR();
- } else {
+ } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::FST_S;
+ else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::FST_D;
+ else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::f2FST_S;
+ else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::f2FST_D;
+ else {
llvm_unreachable("Unknown RegisterClass");
}
@@ -429,7 +449,15 @@ void CSKYInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
} else if (CSKY::CARRYRegClass.hasSubClassEq(RC)) {
Opcode = CSKY::RESTORE_CARRY;
CFI->setSpillsCR();
- } else {
+ } else if (v2sf && CSKY::sFPR32RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::FLD_S;
+ else if (v2df && CSKY::sFPR64RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::FLD_D;
+ else if (v3sf && CSKY::FPR32RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::f2FLD_S;
+ else if (v3df && CSKY::FPR64RegClass.hasSubClassEq(RC))
+ Opcode = CSKY::f2FLD_D;
+ else {
llvm_unreachable("Unknown RegisterClass");
}
@@ -492,6 +520,38 @@ void CSKYInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
unsigned Opcode = 0;
if (CSKY::GPRRegClass.contains(DestReg, SrcReg))
Opcode = CSKY::MOV32;
+ else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg))
+ Opcode = CSKY::FMOV_S;
+ else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg))
+ Opcode = CSKY::f2FMOV_S;
+ else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg))
+ Opcode = CSKY::FMOV_D;
+ else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg))
+ Opcode = CSKY::f2FMOV_D;
+ else if (v2sf && CSKY::sFPR32RegClass.contains(SrcReg) &&
+ CSKY::GPRRegClass.contains(DestReg))
+ Opcode = CSKY::FMFVRL;
+ else if (v3sf && CSKY::FPR32RegClass.contains(SrcReg) &&
+ CSKY::GPRRegClass.contains(DestReg))
+ Opcode = CSKY::f2FMFVRL;
+ else if (v2df && CSKY::sFPR64RegClass.contains(SrcReg) &&
+ CSKY::GPRRegClass.contains(DestReg))
+ Opcode = CSKY::FMFVRL_D;
+ else if (v3df && CSKY::FPR64RegClass.contains(SrcReg) &&
+ CSKY::GPRRegClass.contains(DestReg))
+ Opcode = CSKY::f2FMFVRL_D;
+ else if (v2sf && CSKY::GPRRegClass.contains(SrcReg) &&
+ CSKY::sFPR32RegClass.contains(DestReg))
+ Opcode = CSKY::FMTVRL;
+ else if (v3sf && CSKY::GPRRegClass.contains(SrcReg) &&
+ CSKY::FPR32RegClass.contains(DestReg))
+ Opcode = CSKY::f2FMTVRL;
+ else if (v2df && CSKY::GPRRegClass.contains(SrcReg) &&
+ CSKY::sFPR64RegClass.contains(DestReg))
+ Opcode = CSKY::FMTVRL_D;
+ else if (v3df && CSKY::GPRRegClass.contains(SrcReg) &&
+ CSKY::FPR64RegClass.contains(DestReg))
+ Opcode = CSKY::f2FMTVRL_D;
else {
LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg);
LLVM_DEBUG(I->dump());
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
index fd6501ee48ed9..1a1bbbf9154f7 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h
@@ -24,6 +24,11 @@ namespace llvm {
class CSKYSubtarget;
class CSKYInstrInfo : public CSKYGenInstrInfo {
+ bool v2sf;
+ bool v2df;
+ bool v3sf;
+ bool v3df;
+
protected:
const CSKYSubtarget &STI;
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.td b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
index 2811065cc9832..a782efe7f4f42 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.td
@@ -1360,3 +1360,5 @@ def CONSTPOOL_ENTRY : CSKYPseudo<(outs),
(ins i32imm:$instid, i32imm:$cpidx, i32imm:$size), "", []>;
include "CSKYInstrInfo16Instr.td"
+include "CSKYInstrInfoF1.td"
+include "CSKYInstrInfoF2.td"
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
new file mode 100644
index 0000000000000..30cef024f35ad
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF1.td
@@ -0,0 +1,420 @@
+//===- CSKYInstrInfoF1.td - CSKY Instruction Float1.0 ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the CSKY instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+def regseq_f1 : Operand<iPTR> {
+ let EncoderMethod = "getRegisterSeqOpValue";
+ let ParserMatchClass = RegSeqAsmOperand<"V1">;
+ let PrintMethod = "printRegisterSeq";
+ let DecoderMethod = "DecodeRegSeqOperandF1";
+ let MIOperandInfo = (ops sFPR32, uimm5);
+}
+
+def regseq_d1 : Operand<iPTR> {
+ let EncoderMethod = "getRegisterSeqOpValue";
+ let ParserMatchClass = RegSeqAsmOperand<"V1">;
+ let PrintMethod = "printRegisterSeq";
+ let DecoderMethod = "DecodeRegSeqOperandD1";
+ let MIOperandInfo = (ops sFPR64, uimm5);
+}
+
+def sFPR32Op : RegisterOperand<sFPR32, "printFPR">;
+def sFPR64Op : RegisterOperand<sFPR64, "printFPR">;
+def sFPR64_V_OP : RegisterOperand<sFPR64_V, "printFPR">;
+
+include "CSKYInstrFormatsF1.td"
+
+//===----------------------------------------------------------------------===//
+// CSKY specific DAG Nodes.
+//===----------------------------------------------------------------------===//
+
+def SDT_BITCAST_TO_LOHI : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>]>;
+def CSKY_BITCAST_TO_LOHI : SDNode<"CSKYISD::BITCAST_TO_LOHI", SDT_BITCAST_TO_LOHI>;
+def SDT_BITCAST_FROM_LOHI : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>]>;
+def CSKY_BITCAST_FROM_LOHI : SDNode<"CSKYISD::BITCAST_FROM_LOHI", SDT_BITCAST_FROM_LOHI>;
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def fpimm0 : PatLeaf<(fpimm), [{ return N->isExactlyValue(+0.0); }]>;
+
+def fpimm32_hi16 : SDNodeXForm<fpimm, [{
+ return CurDAG->getTargetConstant(
+ (N->getValueAPF().bitcastToAPInt().getZExtValue() >> 16) & 0xFFFF,
+ SDLoc(N), MVT::i32);
+}]>;
+
+def fpimm32_lo16 : SDNodeXForm<fpimm, [{
+ return CurDAG->getTargetConstant(
+ N->getValueAPF().bitcastToAPInt().getZExtValue() & 0xFFFF,
+ SDLoc(N), MVT::i32);
+}]>;
+
+class fpimm_xform<int width, int shift = 0> : SDNodeXForm<fpimm,
+ "return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i32);">;
+
+class fpimm_xform_i16<int width, int shift = 0> : SDNodeXForm<fpimm,
+ "return CurDAG->getTargetConstant(N->getValueAPF().bitcastToAPInt().lshr("#shift#").getLoBits("#width#"), SDLoc(N), MVT::i16);">;
+
+class fpimm_t<int width, int shift = 0> : PatLeaf<(fpimm),
+ "return isShiftedUInt<"#width#", "#shift#">(N->getValueAPF().bitcastToAPInt().getZExtValue());">;
+
+def fpimm8 : fpimm_t<8>;
+def fpimm8_8 : fpimm_t<8, 8>;
+def fpimm8_16 : fpimm_t<8, 16>;
+def fpimm8_24 : fpimm_t<8, 24>;
+def fpimm16 : fpimm_t<16>;
+def fpimm16_8 : fpimm_t<16, 8>;
+def fpimm16_16 : fpimm_t<16, 16>;
+def fpimm24 : fpimm_t<24>;
+def fpimm24_8 : fpimm_t<24, 8>;
+def fpimm32 : fpimm_t<32>;
+
+def fpimm8_sr0_XFORM : fpimm_xform<8>;
+def fpimm8_sr8_XFORM : fpimm_xform<8, 8>;
+def fpimm8_sr16_XFORM : fpimm_xform<8, 16>;
+def fpimm8_sr24_XFORM : fpimm_xform<8, 24>;
+
+def fpimm8_sr0_i16_XFORM : fpimm_xform_i16<8>;
+def fpimm8_sr8_i16_XFORM : fpimm_xform_i16<8, 8>;
+
+def fconstpool_symbol : Operand<iPTR> {
+ let ParserMatchClass = Constpool;
+ let EncoderMethod =
+ "getConstpoolSymbolOpValue<CSKY::fixup_csky_pcrel_uimm8_scale4>";
+ let DecoderMethod = "decodeUImmOperand<8, 2>";
+ let PrintMethod = "printConstpool";
+ let OperandType = "OPERAND_PCREL";
+}
+
+
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+//arithmetic
+
+def FABSM : F_XZ<0x2, 0b000110, "fabsm", "", UnOpFrag<(fabs node:$Src)>, sFPR64_V_OP>;
+def FNEGM : F_XZ<0x2, 0b000111, "fnegm", "", UnOpFrag<(fneg node:$Src)>, sFPR64_V_OP>;
+def FADDM : F_XYZ<0x2, 0b000000, "faddm", "", BinOpFrag<(fadd node:$LHS, node:$RHS)>, sFPR64_V_OP>;
+def FSUBM : F_XYZ<0x2, 0b000001, "fsubm", "", BinOpFrag<(fsub node:$LHS, node:$RHS)>, sFPR64_V_OP>;
+def FMULM : F_XYZ<0x2, 0b010000, "fmulm", "", BinOpFrag<(fmul node:$LHS, node:$RHS)>, sFPR64_V_OP>;
+def FNMULM : F_XYZ<0x2, 0b010001, "fnmulm", "", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>, sFPR64_V_OP>;
+def FMACM : F_ACCUM_XYZ<0x2, 0b010100, "fmacm", "", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;
+def FMSCM : F_ACCUM_XYZ<0x2, 0b010101, "fmscm", "", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>, sFPR64_V_OP>;
+def FNMACM : F_ACCUM_XYZ<0x2, 0b010110, "fnmacm", "", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>, sFPR64_V_OP>;
+def FNMSCM : F_ACCUM_XYZ<0x2, 0b010111, "fnmscm", "", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>, sFPR64_V_OP>;
+
+def FMOVM : F_MOV<0x2, 0b000100, "fmovm", "", sFPR64_V_OP>;
+
+defm FABS : FT_XZ<0b000110, "fabs", UnOpFrag<(fabs node:$Src)>>;
+defm FNEG : FT_XZ<0b000111, "fneg", UnOpFrag<(fneg node:$Src)>>;
+defm FSQRT : FT_XZ<0b011010, "fsqrt", UnOpFrag<(fsqrt node:$Src)>>;
+
+defm FADD : FT_XYZ<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;
+defm FSUB : FT_XYZ<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;
+defm FDIV : FT_XYZ<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
+defm FMUL : FT_XYZ<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;
+defm FNMUL : FT_XYZ<0b010001, "fnmul", BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
+defm FMAC : FT_ACCUM_XYZ<0b010100, "fmac", TriOpFrag<(fadd node:$LHS, (fmul node:$MHS, node:$RHS))>>;
+defm FMSC : FT_ACCUM_XYZ<0b010101, "fmsc", TriOpFrag<(fsub (fmul node:$MHS, node:$RHS), node:$LHS)>>;
+defm FNMAC : FT_ACCUM_XYZ<0b010110, "fnmac", TriOpFrag<(fsub node:$LHS, (fmul node:$MHS, node:$RHS))>>;
+defm FNMSC : FT_ACCUM_XYZ<0b010111, "fnmsc", TriOpFrag<(fneg (fadd node:$LHS, (fmul node:$MHS, node:$RHS)))>>;
+
+defm FCMPHS : FT_CMPXY<0b001100, "fcmphs">;
+defm FCMPLT : FT_CMPXY<0b001101, "fcmplt">;
+defm FCMPNE : FT_CMPXY<0b001110, "fcmpne">;
+defm FCMPUO : FT_CMPXY<0b001111, "fcmpuo">;
+defm FCMPZHS : FT_CMPZX<0b001000, "fcmpzhs">;
+defm FCMPZLS : FT_CMPZX<0b001001, "fcmpzls">;
+defm FCMPZNE : FT_CMPZX<0b001010, "fcmpzne">;
+defm FCMPZUO : FT_CMPZX<0b001011, "fcmpzuo">;
+
+defm FRECIP : FT_MOV<0b011001, "frecip">;
+
+//fmov, fmtvr, fmfvr
+defm FMOV : FT_MOV<0b000100, "fmov">;
+def FMFVRL : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR32Op:$vrx),
+ "fmfvrl\t$rz, $vrx", [(set GPR:$rz, (bitconvert sFPR32Op:$vrx))]>;
+def FMTVRL : F_XZ_FG<3, 0b011011, (outs sFPR32Op:$vrz), (ins GPR:$rx),
+ "fmtvrl\t$vrz, $rx", [(set sFPR32Op:$vrz, (bitconvert GPR:$rx))]>;
+
+let Predicates = [HasFPUv2_DF] in {
+ let isCodeGenOnly = 1 in
+ def FMFVRL_D : F_XZ_GF<3, 0b011001, (outs GPR:$rz), (ins sFPR64Op:$vrx),
+ "fmfvrl\t$rz, $vrx", []>;
+ def FMFVRH_D : F_XZ_GF<3, 0b011000, (outs GPR:$rz), (ins sFPR64Op:$vrx),
+ "fmfvrh\t$rz, $vrx", []>;
+ let isCodeGenOnly = 1 in
+ def FMTVRL_D : F_XZ_FG<3, 0b011011, (outs sFPR64Op:$vrz), (ins GPR:$rx),
+ "fmtvrl\t$vrz, $rx", []>;
+let Constraints = "$vrZ = $vrz" in
+ def FMTVRH_D : F_XZ_FG<3, 0b011010, (outs sFPR64Op:$vrz), (ins sFPR64Op:$vrZ, GPR:$rx),
+ "fmtvrh\t$vrz, $rx", []>;
+}
+
+//fcvt
+
+def FSITOS : F_XZ_TRANS<0b010000, "fsitos", sFPR32Op, sFPR32Op>;
+def : Pat<(f32 (sint_to_fp GPR:$a)),
+ (FSITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
+ Requires<[HasFPUv2_SF]>;
+
+def FUITOS : F_XZ_TRANS<0b010001, "fuitos", sFPR32Op, sFPR32Op>;
+def : Pat<(f32 (uint_to_fp GPR:$a)),
+ (FUITOS (COPY_TO_REGCLASS GPR:$a, sFPR32))>,
+ Requires<[HasFPUv2_SF]>;
+
+def FSITOD : F_XZ_TRANS<0b010100, "fsitod", sFPR64Op, sFPR64Op>;
+def : Pat<(f64 (sint_to_fp GPR:$a)),
+ (FSITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
+ Requires<[HasFPUv2_DF]>;
+
+def FUITOD : F_XZ_TRANS<0b010101, "fuitod", sFPR64Op, sFPR64Op>;
+def : Pat<(f64 (uint_to_fp GPR:$a)),
+ (FUITOD (COPY_TO_REGCLASS GPR:$a, sFPR64))>,
+ Requires<[HasFPUv2_DF]>;
+
+let Predicates = [HasFPUv2_DF] in {
+def FDTOS : F_XZ_TRANS_DS<0b010110,"fdtos", UnOpFrag<(fpround node:$Src)>>;
+def FSTOD : F_XZ_TRANS_SD<0b010111,"fstod", UnOpFrag<(fpextend node:$Src)>>;
+}
+
+def rpiFSTOSI : F_XZ_TRANS<0b000010, "fstosi.rpi", sFPR32Op, sFPR32Op>;
+def rpiFSTOUI : F_XZ_TRANS<0b000110, "fstoui.rpi", sFPR32Op, sFPR32Op>;
+def rzFSTOSI : F_XZ_TRANS<0b000001, "fstosi.rz", sFPR32Op, sFPR32Op>;
+def rzFSTOUI : F_XZ_TRANS<0b000101, "fstoui.rz", sFPR32Op, sFPR32Op>;
+def rnFSTOSI : F_XZ_TRANS<0b000000, "fstosi.rn", sFPR32Op, sFPR32Op>;
+def rnFSTOUI : F_XZ_TRANS<0b000100, "fstoui.rn", sFPR32Op, sFPR32Op>;
+def rniFSTOSI : F_XZ_TRANS<0b000011, "fstosi.rni", sFPR32Op, sFPR32Op>;
+def rniFSTOUI : F_XZ_TRANS<0b000111, "fstoui.rni", sFPR32Op, sFPR32Op>;
+
+let Predicates = [HasFPUv2_DF] in {
+def rpiFDTOSI : F_XZ_TRANS<0b001010, "fdtosi.rpi", sFPR64Op, sFPR64Op>;
+def rpiFDTOUI : F_XZ_TRANS<0b001110, "fdtoui.rpi", sFPR64Op, sFPR64Op>;
+def rzFDTOSI : F_XZ_TRANS<0b001001, "fdtosi.rz", sFPR64Op, sFPR64Op>;
+def rzFDTOUI : F_XZ_TRANS<0b001101, "fdtoui.rz", sFPR64Op, sFPR64Op>;
+def rnFDTOSI : F_XZ_TRANS<0b001000, "fdtosi.rn", sFPR64Op, sFPR64Op>;
+def rnFDTOUI : F_XZ_TRANS<0b001100, "fdtoui.rn", sFPR64Op, sFPR64Op>;
+def rniFDTOSI : F_XZ_TRANS<0b001011, "fdtosi.rni", sFPR64Op, sFPR64Op>;
+def rniFDTOUI : F_XZ_TRANS<0b001111, "fdtoui.rni", sFPR64Op, sFPR64Op>;
+}
+
+multiclass FPToIntegerPats<SDNode round, string SUFFIX> {
+ def : Pat<(i32 (fp_to_sint (round sFPR32Op:$Rn))),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_SF]>;
+ def : Pat<(i32 (fp_to_uint (round sFPR32Op:$Rn))),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_SF]>;
+ def : Pat<(i32 (fp_to_sint (round sFPR64Op:$Rn))),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_DF]>;
+ def : Pat<(i32 (fp_to_uint (round sFPR64Op:$Rn))),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_DF]>;
+}
+
+defm: FPToIntegerPats<fceil, "rpi">;
+defm: FPToIntegerPats<fround, "rn">;
+defm: FPToIntegerPats<ffloor, "rni">;
+
+multiclass FPToIntegerTowardszeroPats<string SUFFIX> {
+ def : Pat<(i32 (fp_to_sint sFPR32Op:$Rn)),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOSI) sFPR32Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_SF]>;
+ def : Pat<(i32 (fp_to_uint sFPR32Op:$Rn)),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FSTOUI) sFPR32Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_SF]>;
+ def : Pat<(i32 (fp_to_sint sFPR64Op:$Rn)),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOSI) sFPR64Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_DF]>;
+ def : Pat<(i32 (fp_to_uint sFPR64Op:$Rn)),
+ (COPY_TO_REGCLASS (!cast<Instruction>(SUFFIX # FDTOUI) sFPR64Op:$Rn), GPR)>,
+ Requires<[HasFPUv2_DF]>;
+}
+
+defm: FPToIntegerTowardszeroPats<"rz">;
+
+
+//fld, fst
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ defm FLD : FT_XYAI_LD<0b0010000, "fld">;
+ defm FLDR : FT_XYAR_LD<0b0010100, "fldr">;
+ defm FLDM : FT_XYAR_LDM<0b0011000, "fldm">;
+
+ let Predicates = [HasFPUv2_DF] in
+ def FLDRM : F_XYAR_LD<0b0010101, 0, "fldrm", "", sFPR64Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def FLDMM : F_I4_XY_MEM<0b0011001, 0,
+ (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fldmm\t$regs, (${rx})", []>;
+ let Predicates = [HasFPUv2_DF] in
+ def FLDM : F_XYAI_LD<0b0010001, 0, "fldm", "", sFPR64Op, uimm8_3>;
+}
+
+
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ defm FST : FT_XYAI_ST<0b0010010, "fst">;
+ defm FSTR : FT_XYAR_ST<0b0010110, "fstr">;
+ defm FSTM : FT_XYAR_STM<0b0011010, "fstm">;
+
+ let Predicates = [HasFPUv2_DF] in
+ def FSTRM : F_XYAR_ST<0b0010111, 0, "fstrm", "", sFPR64Op>;
+ let Predicates = [HasFPUv2_DF] in
+ def FSTMM : F_I4_XY_MEM<0b0011011, 0,
+ (outs), (ins GPR:$rx, regseq_d1:$regs, variable_ops), "fstmm\t$regs, (${rx})", []>;
+ let Predicates = [HasFPUv2_DF] in
+ def FSTM : F_XYAI_ST<0b0010011, 0, "fstm", "", sFPR64Op, uimm8_3>;
+}
+
+defm : LdPat<load, uimm8_2, FLD_S, f32>, Requires<[HasFPUv2_SF]>;
+defm : LdPat<load, uimm8_2, FLD_D, f64>, Requires<[HasFPUv2_DF]>;
+defm : LdrPat<load, FLDR_S, f32>, Requires<[HasFPUv2_SF]>;
+defm : LdrPat<load, FLDR_D, f64>, Requires<[HasFPUv2_DF]>;
+
+defm : StPat<store, f32, uimm8_2, FST_S>, Requires<[HasFPUv2_SF]>;
+defm : StPat<store, f64, uimm8_2, FST_D>, Requires<[HasFPUv2_DF]>;
+defm : StrPat<store, f32, FSTR_S>, Requires<[HasFPUv2_SF]>;
+defm : StrPat<store, f64, FSTR_D>, Requires<[HasFPUv2_DF]>;
+
+
+def : Pat<(f32 fpimm16:$imm), (COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), sFPR32)>,
+ Requires<[HasFPUv2_SF]>;
+def : Pat<(f32 fpimm16_16:$imm), (f32 (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), sFPR32))>,
+ Requires<[HasFPUv2_SF]>;
+def : Pat<(f32 fpimm:$imm), (COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), sFPR32)>,
+ Requires<[HasFPUv2_SF]>;
+
+def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
+ Requires<[HasFPUv2_DF]>;
+
+multiclass BRCond_Bin<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+ let Predicates = [HasFPUv2_SF] in
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
+ let Predicates = [HasFPUv2_DF] in
+ def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
+
+ let Predicates = [HasFPUv2_SF] in
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2))>;
+ let Predicates = [HasFPUv2_DF] in
+ def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2))>;
+}
+
+multiclass BRCond_Bin_SWAP<CondCode CC, string Instr, Instruction Br, Instruction MV> {
+ let Predicates = [HasFPUv2_SF] in
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1), bb:$imm16)>;
+ let Predicates = [HasFPUv2_DF] in
+ def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1), bb:$imm16)>;
+
+ let Predicates = [HasFPUv2_SF] in
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_S) sFPR32Op:$rs2, sFPR32Op:$rs1))>;
+ let Predicates = [HasFPUv2_DF] in
+ def : Pat<(i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_D) sFPR64Op:$rs2, sFPR64Op:$rs1))>;
+}
+
+// inverse (order && compare) to (unorder || inverse(compare))
+
+defm : BRCond_Bin<SETUNE, "FCMPNE", BT32, MVC32>;
+defm : BRCond_Bin<SETOEQ, "FCMPNE", BF32, MVCV32>;
+defm : BRCond_Bin<SETOGE, "FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin<SETOLT, "FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin<SETUO, "FCMPUO", BT32, MVC32>;
+defm : BRCond_Bin<SETO, "FCMPUO", BF32, MVCV32>;
+defm : BRCond_Bin_SWAP<SETOGT, "FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP<SETOLE, "FCMPHS", BT32, MVC32>;
+
+defm : BRCond_Bin<SETNE, "FCMPNE", BT32, MVC32>;
+defm : BRCond_Bin<SETEQ, "FCMPNE", BF32, MVCV32>;
+defm : BRCond_Bin<SETGE, "FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin<SETLT, "FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP<SETGT, "FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP<SETLE, "FCMPHS", BT32, MVC32>;
+
+// -----------
+
+let Predicates = [HasFPUv2_SF] in {
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
+ (BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGE)),
+ (MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
+ (BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLT)),
+ (MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16),
+ (BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOLE)),
+ (MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),
+ (BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOGT)),
+ (MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),
+ (BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETUNE)),
+ (MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),
+ (BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETOEQ)),
+ (MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)), bb:$imm16),
+ (BT32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETUO)),
+ (MVC32 (FCMPZUO_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm, SETO)), bb:$imm16),
+ (BF32 (FCMPZUO_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm, SETO)),
+ (MVCV32 (FCMPZUO_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
+ (BT32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGE)),
+ (MVC32 (FCMPZHS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
+ (BF32 (FCMPZHS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLT)),
+ (MVCV32 (FCMPZHS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)), bb:$imm16),
+ (BT32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETLE)),
+ (MVC32 (FCMPZLS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
+ (BF32 (FCMPZLS_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETGT)),
+ (MVCV32 (FCMPZLS_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)), bb:$imm16),
+ (BT32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETNE)),
+ (MVC32 (FCMPZNE_S sFPR32Op:$rs1))>;
+ def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
+ (BF32 (FCMPZNE_S sFPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc sFPR32Op:$rs1, fpimm0, SETEQ)),
+ (MVCV32 (FCMPZNE_S sFPR32Op:$rs1))>;
+}
+
+let usesCustomInserter = 1 in {
+ let Predicates = [HasFPUv2_SF] in
+ def FSELS : CSKYPseudo<(outs sFPR32Op:$dst), (ins CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2),
+ "!fsels\t$dst, $src1, src2", [(set sFPR32Op:$dst, (select CARRY:$cond, sFPR32Op:$src1, sFPR32Op:$src2))]>;
+
+ let Predicates = [HasFPUv2_DF] in
+ def FSELD : CSKYPseudo<(outs sFPR64Op:$dst), (ins CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2),
+ "!fseld\t$dst, $src1, src2", [(set sFPR64Op:$dst, (select CARRY:$cond, sFPR64Op:$src1, sFPR64Op:$src2))]>;
+}
\ No newline at end of file
diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
new file mode 100644
index 0000000000000..8a00e7d9af3a7
--- /dev/null
+++ b/llvm/lib/Target/CSKY/CSKYInstrInfoF2.td
@@ -0,0 +1,462 @@
+//===- CSKYInstrInfoF2.td - CSKY Instruction Float2.0 ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the CSKY instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
+def regseq_f2 : Operand<i32> {
+ let EncoderMethod = "getRegisterSeqOpValue";
+ let ParserMatchClass = RegSeqAsmOperand<"V2">;
+ let PrintMethod = "printRegisterSeq";
+ let DecoderMethod = "DecodeRegSeqOperandF2";
+ let MIOperandInfo = (ops FPR32, uimm5);
+}
+
+def regseq_d2 : Operand<i32> {
+ let EncoderMethod = "getRegisterSeqOpValue";
+ let ParserMatchClass = RegSeqAsmOperand<"V2">;
+ let PrintMethod = "printRegisterSeq";
+ let DecoderMethod = "DecodeRegSeqOperandD2";
+ let MIOperandInfo = (ops FPR64, uimm5);
+}
+
+def FPR32Op : RegisterOperand<FPR32, "printFPR">;
+def FPR64Op : RegisterOperand<FPR64, "printFPR">;
+
+include "CSKYInstrFormatsF2.td"
+
+// Predicates
+def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{
+ return isOrEquivalentToAdd(N);
+}]>;
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+defm f2FADD : F2_XYZ_T<0b000000, "fadd", BinOpFrag<(fadd node:$LHS, node:$RHS)>>;
+defm f2FSUB : F2_XYZ_T<0b000001, "fsub", BinOpFrag<(fsub node:$LHS, node:$RHS)>>;
+defm f2FDIV : F2_XYZ_T<0b011000, "fdiv", BinOpFrag<(fdiv node:$LHS, node:$RHS)>>;
+defm f2FMUL : F2_XYZ_T<0b010000, "fmul", BinOpFrag<(fmul node:$LHS, node:$RHS)>>;
+
+defm f2FMAXNM : F2_XYZ_T<0b101000, "fmaxnm", BinOpFrag<(fmaxnum node:$LHS, node:$RHS)>>;
+defm f2FMINNM : F2_XYZ_T<0b101001, "fminnm", BinOpFrag<(fminnum node:$LHS, node:$RHS)>>;
+
+defm f2FABS : F2_XZ_T<0b000110, "fabs", fabs>;
+defm f2FNEG : F2_XZ_T<0b000111, "fneg", fneg>;
+defm f2FSQRT : F2_XZ_T<0b011010, "fsqrt", fsqrt>;
+defm f2FMOV : F2_XZ_SET_T<0b000100, "fmov">;
+def f2FMOVX : F2_XZ_SET<0b00001, FPR32Op, 0b000101, "fmovx.32">;
+
+defm f2RECIP : F2_XZ_SET_T<0b011001, "frecip">;
+
+// fld/fst
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def f2FLD_S : F2_LDST_S<0b0, "fld", (outs FPR32Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FLD_D : F2_LDST_D<0b0, "fld", (outs FPR64Op:$vrz), (ins GPR:$rx, uimm8_2:$imm8)>;
+}
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ def f2FST_S : F2_LDST_S<0b1, "fst", (outs), (ins FPR32Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FST_D : F2_LDST_D<0b1, "fst", (outs), (ins FPR64Op:$vrz, GPR:$rx, uimm8_2:$imm8)>;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ def f2FSTM_S : F2_LDSTM_S<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FSTM_D : F2_LDSTM_D<0b1, 0, "fstm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
+
+ def f2FSTMU_S : F2_LDSTM_S<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FSTMU_D : F2_LDSTM_D<0b1, 0b100, "fstmu", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
+}
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def f2FLDM_S : F2_LDSTM_S<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FLDM_D : F2_LDSTM_D<0b0, 0, "fldm", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
+
+ def f2FLDMU_S : F2_LDSTM_S<0b0, 0b100, "fldmu", (outs), (ins GPR:$rx, regseq_f2:$regs, variable_ops)>;
+ let Predicates = [HasFPUv3_DF] in
+ def f2FLDMU_D : F2_LDSTM_D<0b0, 0b100, "fldmu", (outs), (ins GPR:$rx, regseq_d2:$regs, variable_ops)>;
+}
+
+multiclass FLSR {
+ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+ def FLDR_S : F2_LDSTR_S<0b0, "fldr", (outs FPR32Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>;
+ let Predicates = [HasFPUv3_DF] in
+ def FLDR_D : F2_LDSTR_D<0b0, "fldr", (outs FPR64Op:$rz), (ins GPR:$rx, GPR:$ry, uimm2:$imm)>;
+ }
+ let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+ def FSTR_S : F2_LDSTR_S<0b1, "fstr", (outs), (ins FPR32Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>;
+ let Predicates = [HasFPUv3_DF] in
+ def FSTR_D : F2_LDSTR_D<0b1, "fstr", (outs), (ins FPR64Op:$rz, GPR:$rx, GPR:$ry, uimm2:$imm)>;
+ }
+}
+
+defm f2: FLSR;
+
+def f2FLRW_S : F2_LRW<0b00, 0b0, "flrw.32", (outs FPR32Op:$vrz), (ins fconstpool_symbol:$imm8)>;
+def f2FLRW_D : F2_LRW<0b01, 0b0, "flrw.64", (outs FPR64Op:$vrz), (ins fconstpool_symbol:$imm8)>;
+
+def : Pat<(f32 (load constpool:$src)), (f2FLRW_S (to_tconstpool tconstpool:$src))>, Requires<[HasFPUv3_SF]>;
+def : Pat<(f64 (load constpool:$src)), (f2FLRW_D (to_tconstpool tconstpool:$src))>, Requires<[HasFPUv3_DF]>;
+
+defm : LdPat<load, uimm8_2, f2FLD_S, f32>, Requires<[HasFPUv3_SF]>;
+defm : LdPat<load, uimm8_2, f2FLD_D, f64>, Requires<[HasFPUv3_DF]>;
+defm : LdrPat<load, f2FLDR_S, f32>, Requires<[HasFPUv3_SF]>;
+defm : LdrPat<load, f2FLDR_D, f64>, Requires<[HasFPUv3_DF]>;
+
+defm : StPat<store, f32, uimm8_2, f2FST_S>, Requires<[HasFPUv3_SF]>;
+defm : StPat<store, f64, uimm8_2, f2FST_D>, Requires<[HasFPUv3_DF]>;
+defm : StrPat<store, f32, f2FSTR_S>, Requires<[HasFPUv3_SF]>;
+defm : StrPat<store, f64, f2FSTR_D>, Requires<[HasFPUv3_DF]>;
+
+// fmfvr
+let vry = 0 in
+def f2FMFVRL : F2_XYZ<0b00011, 0b011001, "fmfvr.32.1\t$vrz, $vrx",
+ (outs GPR:$vrz), (ins FPR32Op:$vrx),
+ [(set GPR:$vrz, (bitconvert FPR32Op:$vrx))]>;
+// TODO: vrz and vrz+1
+def f2FMFVRL_2 : F2_XYZ<0b00011, 0b111010, "fmfvr.32.2\t$vrz, $vry, $vrx",
+ (outs GPR:$vrz, GPR:$vry), (ins FPR64Op:$vrx),
+ []>;
+
+let Predicates = [HasFPUv3_DF] in {
+let vry = 0 in {
+let isCodeGenOnly = 1 in
+def f2FMFVRL_D : F2_XYZ<0b00011, 0b011001, "fmfvr.32.1\t$vrz, $vrx",
+ (outs GPR:$vrz), (ins FPR64Op:$vrx),
+ []>;
+def f2FMFVRH_D : F2_XYZ<0b00011, 0b011000, "fmfvrh\t$vrz, $vrx",
+ (outs GPR:$vrz), (ins FPR64Op:$vrx),
+ []>;
+}
+def f2FMFVR_D : F2_XYZ<0b00011, 0b111000, "fmfvr.64\t$vrz, $vry, $vrx",
+ (outs GPR:$vrz, GPR:$vry), (ins FPR64Op:$vrx),
+ [(set GPR:$vrz, GPR:$vry, (CSKY_BITCAST_TO_LOHI FPR64Op:$vrx))]>;
+}
+
+// fmtvr
+def f2FMTVRL : F2_XZ_P<0b00011, 0b011011, "fmtvr.32.1",
+ [(set FPR32Op:$vrz, (bitconvert GPR:$vrx))],
+ (outs FPR32Op:$vrz), (ins GPR:$vrx)>;
+// TODO: vrz and vrz+1
+def f2FMTVRL_2 : F2_XYZ<0b00011, 0b111110, "fmtvr.32.2\t$vrz, $vrx, $vry",
+ (outs FPR32Op:$vrz), (ins GPR:$vrx, GPR:$vry),
+ []>;
+
+let Predicates = [HasFPUv3_DF] in {
+let isCodeGenOnly = 1 in
+def f2FMTVRL_D : F2_XZ_P<0b00011, 0b011011, "fmtvr.32.1",
+ [],
+ (outs FPR64Op:$vrz), (ins GPR:$vrx)>;
+let Constraints = "$vrZ = $vrz" in
+def f2FMTVRH_D : F2_XZ_P<0b00011, 0b011010, "fmtvrh",
+ [],
+ (outs FPR64Op:$vrz), (ins FPR64Op:$vrZ, GPR:$vrx)>;
+def f2FMTVR_D : F2_XYZ<0b00011, 0b111100, "fmtvr.64\t$vrz, $vrx, $vry",
+ (outs FPR64Op:$vrz), (ins GPR:$vrx, GPR:$vry),
+ [(set FPR64Op:$vrz, (CSKY_BITCAST_FROM_LOHI GPR:$vrx, GPR:$vry))]>;
+}
+
+// fcmp
+
+defm f2FCMPHS: F2_CXY_T<0b001100, "fcmphs">;
+defm f2FCMPLT: F2_CXY_T<0b001101, "fcmplt">;
+defm f2FCMPNE: F2_CXY_T<0b001110, "fcmpne">;
+defm f2FCMPUO: F2_CXY_T<0b001111, "fcmpuo">;
+
+defm f2FCMPHSZ: F2_CX_T<0b001000, "fcmphsz">;
+defm f2FCMPHZ : F2_CX_T<0b101010, "fcmphz">;
+defm f2FCMPLSZ: F2_CX_T<0b101011, "fcmplsz">;
+defm f2FCMPLTZ: F2_CX_T<0b001001, "fcmpltz">;
+defm f2FCMPNEZ: F2_CX_T<0b001010, "fcmpnez">;
+defm f2FCMPUOZ: F2_CX_T<0b001011, "fcmpuoz">;
+
+defm f2FMULA : F2_XYZZ_T<0b010100, "fmula",
+ TriOpFrag<(fadd (fmul node:$LHS, node:$MHS), node:$RHS)>>;
+
+defm f2FMULS : F2_XYZZ_T<0b010110, "fmuls",
+ TriOpFrag<(fsub node:$RHS, (fmul node:$LHS, node:$MHS))>>;
+
+defm f2FFMULA : F2_XYZZ_T<0b110000, "ffmula",
+ TriOpFrag<(fma node:$LHS, node:$MHS, node:$RHS)>>;
+
+defm f2FFMULS : F2_XYZZ_T<0b110001, "ffmuls",
+ TriOpFrag<(fma (fneg node:$LHS), node:$MHS, node:$RHS)>>;
+
+defm f2FFNMULA : F2_XYZZ_T<0b110010, "ffnmula",
+ TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))>>;
+
+defm f2FFNMULS : F2_XYZZ_T<0b110011, "ffnmuls",
+ TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))>>;
+
+defm f2FNMULA : F2_XYZZ_T<0b010111, "fnmula",
+ TriOpFrag<(fneg (fadd (fmul node:$LHS, node:$MHS), node:$RHS))>>;
+
+defm f2FNMULS : F2_XYZZ_T<0b010101, "fnmuls",
+ TriOpFrag<(fneg (fsub node:$RHS, (fmul node:$LHS, node:$MHS)))>>;
+
+defm f2FNMUL : F2_XYZ_T<0b010001, "fnmul",
+ BinOpFrag<(fneg (fmul node:$LHS, node:$RHS))>>;
+
+// fcvt
+def f2FFTOS32_S : F2_XZ_P<0b01000, 0b011011, "fftoi.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FFTOU32_S : F2_XZ_P<0b01000, 0b011010, "fftoi.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FS32TOF_S : F2_XZ_P<0b01001, 0b011011, "fitof.s32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FU32TOF_S : F2_XZ_P<0b01001, 0b011010, "fitof.u32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FFTOXU32_S : F2_XZ_P<0b01000, 0b001010, "fftox.f32.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FFTOXS32_S : F2_XZ_P<0b01000, 0b001011, "fftox.f32.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FXTOFU32_S : F2_XZ_P<0b01001, 0b001010, "fxtof.u32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FXTOFS32_S : F2_XZ_P<0b01001, 0b001011, "fxtof.s32.f32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+let Predicates = [HasFPUv3_DF] in {
+def f2FFTOS32_D : F2_XZ_P<0b01000, 0b011101, "fftoi.f64.s32", [], (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
+def f2FFTOU32_D : F2_XZ_P<0b01000, 0b011100, "fftoi.f64.u32", [], (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
+def f2FS32TOF_D : F2_XZ_P<0b01001, 0b011101, "fitof.s32.f64", [], (outs FPR64Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FU32TOF_D : F2_XZ_P<0b01001, 0b011100, "fitof.u32.f64", [], (outs FPR64Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FFTOXU32_D : F2_XZ_P<0b01000, 0b001100, "fftox.f64.u32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FFTOXS32_D : F2_XZ_P<0b01000, 0b001101, "fftox.f64.s32", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FXTOFU32_D : F2_XZ_P<0b01001, 0b001100, "fxtof.u32.f64", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+def f2FXTOFS32_D : F2_XZ_P<0b01001, 0b001101, "fxtof.s32.f64", [], (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+}
+
+defm f2FF32TOSI32 : F2_XZ_RM<0b00011, 0b0000, "fftoi.f32.s32", (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+defm f2FF32TOUI32 : F2_XZ_RM<0b00011, 0b0001, "fftoi.f32.u32", (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+defm f2FF32TOFI32 : F2_XZ_RM<0b01000, 0b1001, "fftofi.f32", (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+let Predicates = [HasFPUv3_DF] in {
+defm f2FF64TOSI32 : F2_XZ_RM<0b00011, 0b0010, "fftoi.f64.s32", (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
+defm f2FF64TOUI32 : F2_XZ_RM<0b00011, 0b0011, "fftoi.f64.u32", (outs FPR32Op:$vrz), (ins FPR64Op:$vrx)>;
+defm f2FF64TOFI32 : F2_XZ_RM<0b01000, 0b1010, "fftofi.f64", (outs FPR32Op:$vrz), (ins FPR32Op:$vrx)>;
+}
+
+def : Pat<(i32 (fp_to_sint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_uint (fround FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RN $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_sint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_uint (fceil FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_sint (ffloor FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_uint (ffloor FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_sint (ftrunc FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOSI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_uint (ftrunc FPR32Op:$vrx))), (COPY_TO_REGCLASS (f2FF32TOUI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_sint FPR32Op:$vrx)), (COPY_TO_REGCLASS (f2FF32TOSI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+def : Pat<(i32 (fp_to_uint FPR32Op:$vrx)), (COPY_TO_REGCLASS (f2FF32TOUI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_SF]>;
+
+def : Pat<(i32 (fp_to_sint (fround FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOSI32_RN $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_uint (fround FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOUI32_RN $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_sint (fceil FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOSI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_uint (fceil FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOUI32_RPI $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_sint (ffloor FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOSI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_uint (ffloor FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOUI32_RNI $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_sint (ftrunc FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOSI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_uint (ftrunc FPR64Op:$vrx))), (COPY_TO_REGCLASS (f2FF64TOUI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_sint FPR64Op:$vrx)), (COPY_TO_REGCLASS (f2FF64TOSI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+def : Pat<(i32 (fp_to_uint FPR64Op:$vrx)), (COPY_TO_REGCLASS (f2FF64TOUI32_RZ $vrx), GPR)>, Requires<[HasFPUv3_DF]>;
+
+def : Pat<(sint_to_fp GPR:$vrx), (f2FS32TOF_S (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_SF]>;
+def : Pat<(uint_to_fp GPR:$vrx), (f2FU32TOF_S (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_SF]>;
+def : Pat<(sint_to_fp GPR:$vrx), (f2FS32TOF_D (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_DF]>;
+def : Pat<(uint_to_fp GPR:$vrx), (f2FU32TOF_D (COPY_TO_REGCLASS $vrx, FPR32))>, Requires<[HasFPUv3_DF]>;
+
+let Predicates = [HasFPUv3_DF] in {
+def f2FDTOS : F2_XZ_P<0b00011, 0b010110, "fdtos", [(set FPR32Op:$vrz, (fpround FPR64Op:$vrx))], (outs FPR32Op:$vrz),
+ (ins FPR64Op:$vrx)>;
+def f2FSTOD : F2_XZ_P<0b00011, 0b010111, "fstod", [(set FPR64Op:$vrz, (fpextend FPR32Op:$vrx))], (outs FPR64Op:$vrz),
+ (ins FPR32Op:$vrx)>;
+}
+
+// fsel
+defm f2FSEL: F2_CXYZ_T<0b111001, "fsel">;
+
+def f2FINS: F2_XZ_SET<0b00000, FPR32Op, 0b011011, "fins.32">;
+
+def : Pat<(f32 fpimm16:$imm),(COPY_TO_REGCLASS (MOVI32 (fpimm32_lo16 fpimm16:$imm)), FPR32)>,
+ Requires<[HasFPUv3_SF]>;
+def : Pat<(f32 fpimm16_16:$imm), (COPY_TO_REGCLASS (MOVIH32 (fpimm32_hi16 fpimm16_16:$imm)), FPR32)>,
+ Requires<[HasFPUv3_SF]>;
+def : Pat<(f32 fpimm:$imm),(COPY_TO_REGCLASS (ORI32 (MOVIH32 (fpimm32_hi16 fpimm:$imm)), (fpimm32_lo16 fpimm:$imm)), FPR32)>,
+ Requires<[HasFPUv3_SF]>;
+
+
+multiclass BRCond_Bin_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+ let Predicates = [HasFPUv3_SF] in
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
+ let Predicates = [HasFPUv3_DF] in
+ def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
+
+ let Predicates = [HasFPUv3_SF] in
+ def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2))>;
+ let Predicates = [HasFPUv3_DF] in
+ def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2))>;
+
+ let Predicates = [HasFPUv3_SF] in {
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), FPR32Op:$rx, FPR32Op:$false),
+ !if(
+ !eq(IsSelectSwap, 0),
+ (f2FSEL_S (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), FPR32Op:$false, FPR32Op:$rx)
+ )>;
+ }
+ let Predicates = [HasFPUv3_DF] in {
+ def : Pat<(select (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), FPR64Op:$rx, FPR64Op:$false),
+ !if(
+ !eq(IsSelectSwap, 0),
+ (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$rx, FPR64Op:$false),
+ (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), FPR64Op:$false, FPR64Op:$rx)
+ )>;
+ }
+}
+
+multiclass BRCond_Bin_SWAP_F2<CondCode CC, string Instr, Instruction Br, Instruction MV, bit IsSelectSwap = 0> {
+ let Predicates = [HasFPUv3_SF] in
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), bb:$imm16)>;
+ let Predicates = [HasFPUv3_DF] in
+ def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
+ (Br (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), bb:$imm16)>;
+
+ let Predicates = [HasFPUv3_SF] in
+ def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1))>;
+ let Predicates = [HasFPUv3_DF] in
+ def : Pat<(i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)),
+ (MV (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1))>;
+
+ let Predicates = [HasFPUv3_SF] in {
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), FPR32Op:$rx, FPR32Op:$false),
+ !if(
+ !eq(IsSelectSwap, 0),
+ (f2FSEL_S (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (!cast<Instruction>(Instr#_S) FPR32Op:$rs2, FPR32Op:$rs1), FPR32Op:$false, FPR32Op:$rx)
+ )>;
+ }
+ let Predicates = [HasFPUv3_DF] in {
+ def : Pat<(select (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), FPR64Op:$rx, FPR64Op:$false),
+ !if(
+ !eq(IsSelectSwap, 0),
+ (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$rx, FPR64Op:$false),
+ (f2FSEL_D (!cast<Instruction>(Instr#_D) FPR64Op:$rs2, FPR64Op:$rs1), FPR64Op:$false, FPR64Op:$rx)
+ )>;
+ }
+}
+
+// inverse (order && compare) to (unorder || inverse(compare))
+
+defm : BRCond_Bin_F2<SETUNE, "f2FCMPNE", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETOEQ, "f2FCMPNE", BF32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETOGE, "f2FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETOLT, "f2FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETUO, "f2FCMPUO", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETO, "f2FCMPUO", BF32, MVCV32, 1>;
+defm : BRCond_Bin_SWAP_F2<SETOGT, "f2FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETOLE, "f2FCMPHS", BT32, MVC32>;
+
+defm : BRCond_Bin_F2<SETNE, "f2FCMPNE", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETEQ, "f2FCMPNE", BF32, MVCV32, 1>;
+defm : BRCond_Bin_F2<SETGE, "f2FCMPHS", BT32, MVC32>;
+defm : BRCond_Bin_F2<SETLT, "f2FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETGT, "f2FCMPLT", BT32, MVC32>;
+defm : BRCond_Bin_SWAP_F2<SETLE, "f2FCMPHS", BT32, MVC32>;
+
+// ------
+
+let Predicates = [HasFPUv3_SF] in {
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), bb:$imm16),
+ (BT32 (f2FCMPHSZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)),
+ (MVC32 (f2FCMPHSZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGE)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPHSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), bb:$imm16),
+ (BT32 (f2FCMPLTZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)),
+ (MVC32 (f2FCMPLTZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLT)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPLTZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)), bb:$imm16),
+ (BT32 (f2FCMPLSZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)),
+ (MVC32 (f2FCMPLSZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOLE)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPLSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), bb:$imm16),
+ (BT32 (f2FCMPHZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)),
+ (MVC32 (f2FCMPHZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOGT)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPHZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)), bb:$imm16),
+ (BT32 (f2FCMPNEZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)),
+ (MVC32 (f2FCMPNEZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETUNE)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPNEZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm, SETUO)), bb:$imm16),
+ (BT32 (f2FCMPUOZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm, SETUO)),
+ (MVC32 (f2FCMPUOZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm, SETUO)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPUOZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), bb:$imm16),
+ (BT32 (f2FCMPHSZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)),
+ (MVC32 (f2FCMPHSZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGE)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPHSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), bb:$imm16),
+ (BT32 (f2FCMPLTZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)),
+ (MVC32 (f2FCMPLTZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLT)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPLTZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETLE)), bb:$imm16),
+ (BT32 (f2FCMPLSZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETLE)),
+ (MVC32 (f2FCMPLSZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETLE)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPLSZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), bb:$imm16),
+ (BT32 (f2FCMPHZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)),
+ (MVC32 (f2FCMPHZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETGT)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPHZ_S FPR32Op:$rs1), FPR32Op:$rx, FPR32Op:$false)>;
+
+
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm, SETO)), bb:$imm16),
+ (BF32 (f2FCMPUOZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm, SETO)),
+ (MVCV32 (f2FCMPUOZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm, SETO)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPUOZ_S FPR32Op:$rs1), FPR32Op:$false, FPR32Op:$rx)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)), bb:$imm16),
+ (BF32 (f2FCMPNEZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)),
+ (MVCV32 (f2FCMPNEZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETOEQ)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPNEZ_S FPR32Op:$rs1), FPR32Op:$false, FPR32Op:$rx)>;
+ def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), bb:$imm16),
+ (BF32 (f2FCMPNEZ_S FPR32Op:$rs1), bb:$imm16)>;
+ def : Pat<(i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)),
+ (MVCV32 (f2FCMPNEZ_S FPR32Op:$rs1))>;
+ def : Pat<(select (i32 (setcc FPR32Op:$rs1, fpimm0, SETEQ)), FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S (f2FCMPNEZ_S FPR32Op:$rs1), FPR32Op:$false, FPR32Op:$rx)>;
+}
+
+
+let Predicates = [HasFPUv3_SF] in
+def : Pat<(select CARRY:$ca, FPR32Op:$rx, FPR32Op:$false),
+ (f2FSEL_S CARRY:$ca, FPR32Op:$rx, FPR32Op:$false)>;
+let Predicates = [HasFPUv3_DF] in
+def : Pat<(select CARRY:$ca, FPR64Op:$rx, FPR64Op:$false),
+ (f2FSEL_D CARRY:$ca, FPR64Op:$rx, FPR64Op:$false)>;
\ No newline at end of file
diff --git a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
index ade5c7f795af2..b7f4fc17166b9 100644
--- a/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
+++ b/llvm/lib/Target/CSKY/CSKYRegisterInfo.td
@@ -194,6 +194,8 @@ def FPR64 : RegisterClass<"CSKY", [f64], 64,
def sFPR64 : RegisterClass<"CSKY", [f64], 64,
(add (sequence "F%u_64", 0, 15))>;
+def sFPR64_V : RegisterClass<"CSKY", [v2f32], 32, (add sFPR64)>;
+
def FPR128 : RegisterClass<"CSKY",
[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128,
(add (sequence "F%u_128", 0, 31))>;
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
index 7001de999a510..07757f03c258b 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.cpp
@@ -73,6 +73,13 @@ void CSKYInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
O << getRegisterName(RegNo);
}
+void CSKYInstPrinter::printFPRRegName(raw_ostream &O, unsigned RegNo) const {
+ if (PrintBranchImmAsAddress)
+ O << getRegisterName(RegNo, CSKY::NoRegAltName);
+ else
+ O << getRegisterName(RegNo);
+}
+
void CSKYInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O,
const char *Modifier) {
@@ -201,3 +208,11 @@ const char *CSKYInstPrinter::getRegisterName(unsigned RegNo) {
return getRegisterName(RegNo, ArchRegNames ? CSKY::NoRegAltName
: CSKY::ABIRegAltName);
}
+
+void CSKYInstPrinter::printFPR(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O) {
+ const MCOperand &MO = MI->getOperand(OpNo);
+ assert(MO.isReg());
+
+ printFPRRegName(O, MO.getReg());
+}
diff --git a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h
index f93a342ec6a39..52a1b92767625 100644
--- a/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h
+++ b/llvm/lib/Target/CSKY/MCTargetDesc/CSKYInstPrinter.h
@@ -36,6 +36,8 @@ class CSKYInstPrinter : public MCInstPrinter {
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier = nullptr);
+ void printFPRRegName(raw_ostream &O, unsigned RegNo) const;
+
// Autogenerated by tblgen.
std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
void printInstruction(const MCInst *MI, uint64_t Address,
@@ -60,6 +62,8 @@ class CSKYInstPrinter : public MCInstPrinter {
const MCSubtargetInfo &STI, raw_ostream &O);
void printSPAddr(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
+ void printFPR(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
static const char *getRegisterName(unsigned RegNo);
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
};
diff --git a/llvm/test/CodeGen/CSKY/br.ll b/llvm/test/CodeGen/CSKY/br.ll
index af596aebc3005..35f9a4febbd0b 100644
--- a/llvm/test/CodeGen/CSKY/br.ll
+++ b/llvm/test/CodeGen/CSKY/br.ll
@@ -3015,7 +3015,8 @@ define i1 @brRI_i1_eq(i1 %x) {
; CHECK-LABEL: brRI_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bez32 a0, .LBB117_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bf32 .LBB117_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
@@ -3035,7 +3036,8 @@ define i1 @brR0_i1_eq(i1 %x) {
; CHECK-LABEL: brR0_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bez32 a0, .LBB118_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bf32 .LBB118_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: rts16
@@ -3309,7 +3311,8 @@ define i1 @brRI_i1_ule(i1 %x) {
; CHECK-LABEL: brRI_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bnez32 a0, .LBB130_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB130_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -3331,7 +3334,8 @@ define i1 @brR0_i1_ule(i1 %x) {
; CHECK-LABEL: brR0_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bnez32 a0, .LBB131_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB131_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -3449,7 +3453,8 @@ define i1 @brRI_i1_sge(i1 %x) {
; CHECK-LABEL: brRI_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bnez32 a0, .LBB136_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB136_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
@@ -3471,7 +3476,8 @@ define i1 @brR0_i1_sge(i1 %x) {
; CHECK-LABEL: brR0_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
-; CHECK-NEXT: bnez32 a0, .LBB137_2
+; CHECK-NEXT: btsti32 a0, 0
+; CHECK-NEXT: bt32 .LBB137_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: rts16
diff --git a/llvm/test/CodeGen/CSKY/fpu/base-d.ll b/llvm/test/CodeGen/CSKY/fpu/base-d.ll
new file mode 100644
index 0000000000000..d2d434631f62c
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/base-d.ll
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
+
+define double @FADD_DOUBLE(double %x, double %y) {
+; CHECK-DF-LABEL: FADD_DOUBLE:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: faddd vr0, vr1, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FADD_DOUBLE:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fadd.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fadd = fadd double %y, %x
+ ret double %fadd
+}
+
+define double @FADD_DOUBLE_I(double %x) {
+; CHECK-DF-LABEL: FADD_DOUBLE_I:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI1_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: faddd vr0, vr0, vr1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI1_0:
+; CHECK-DF-NEXT: .quad 0xbff0000000000000 # double -1
+;
+; CHECK-DF2-LABEL: FADD_DOUBLE_I:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI1_0]
+; CHECK-DF2-NEXT: fadd.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI1_0:
+; CHECK-DF2-NEXT: .quad 0xbff0000000000000 # double -1
+entry:
+ %fadd = fadd double %x, -1.0
+ ret double %fadd
+}
+
+define double @FSUB_DOUBLE(double %x, double %y) {
+; CHECK-DF-LABEL: FSUB_DOUBLE:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fsubd vr0, vr1, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FSUB_DOUBLE:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fsub.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT: rts16
+
+entry:
+ %fsub = fsub double %y, %x
+ ret double %fsub
+}
+
+define double @FSUB_DOUBLE_I(double %x) {
+;
+; CHECK-DF-LABEL: FSUB_DOUBLE_I:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI3_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: faddd vr0, vr0, vr1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI3_0:
+; CHECK-DF-NEXT: .quad 0x3ff0000000000000 # double 1
+;
+; CHECK-DF2-LABEL: FSUB_DOUBLE_I:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI3_0]
+; CHECK-DF2-NEXT: fadd.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI3_0:
+; CHECK-DF2-NEXT: .quad 0x3ff0000000000000 # double 1
+
+entry:
+ %fsub = fsub double %x, -1.0
+ ret double %fsub
+}
+
+define double @FMUL_DOUBLE(double %x, double %y) {
+;
+; CHECK-DF-LABEL: FMUL_DOUBLE:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fmuld vr0, vr1, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FMUL_DOUBLE:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fmul.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fmul = fmul double %y, %x
+ ret double %fmul
+}
+
+define double @FMUL_DOUBLE_I(double %x) {
+;
+; CHECK-DF-LABEL: FMUL_DOUBLE_I:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fmuld vr0, vr0, vr1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI5_0:
+; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
+;
+; CHECK-DF2-LABEL: FMUL_DOUBLE_I:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT: fmul.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI5_0:
+; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
+entry:
+ %fmul = fmul double %x, -7.0
+ ret double %fmul
+}
+
+define double @FDIV_DOUBLE(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FDIV_DOUBLE:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdivd vr0, vr1, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FDIV_DOUBLE:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fdiv.64 vr0, vr1, vr0
+; CHECK-DF2-NEXT: rts16
+
+entry:
+ %fdiv = fdiv double %y, %x
+ ret double %fdiv
+}
+
+define double @FDIV_DOUBLE_I(double %x) {
+;
+; CHECK-DF-LABEL: FDIV_DOUBLE_I:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fdivd vr0, vr0, vr1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI7_0:
+; CHECK-DF-NEXT: .quad 0xc01c000000000000 # double -7
+;
+; CHECK-DF2-LABEL: FDIV_DOUBLE_I:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT: fdiv.64 vr0, vr0, vr1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI7_0:
+; CHECK-DF2-NEXT: .quad 0xc01c000000000000 # double -7
+entry:
+ %fdiv = fdiv double %x, -7.0
+ ret double %fdiv
+}
+
+define double @FNEG_DOUBLE(double %x) {
+;
+; CHECK-DF-LABEL: FNEG_DOUBLE:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fnegd vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FNEG_DOUBLE:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fneg.64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fneg = fneg double %x
+ ret double %fneg
+}
+
+; double --> float
+define float @fptruncR_double_0(double %x) {
+;
+; CHECK-DF-LABEL: fptruncR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtos vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptruncR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fdtos vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptrunc = fptrunc double %x to float
+ ret float %fptrunc
+}
+
+define double @fpextR_double_0(float %x) {
+;
+; CHECK-DF-LABEL: fpextR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fstod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fpextR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fstod vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fpext = fpext float %x to double
+ ret double %fpext
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/base-f.ll b/llvm/test/CodeGen/CSKY/fpu/base-f.ll
new file mode 100644
index 0000000000000..cd43cc451716a
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/base-f.ll
@@ -0,0 +1,269 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
+
+
+define float @faddRR(float %x, float %y) {
+;
+; CHECK-SF-LABEL: faddRR:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fadds vr0, vr1, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: faddRR:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fadd.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fadd = fadd float %y, %x
+ ret float %fadd
+}
+
+define float @faddRI(float %x) {
+;
+; CHECK-SF-LABEL: faddRI:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fadds vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: faddRI:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fadd = fadd float %x, 10.0
+ ret float %fadd
+}
+
+define float @faddRI_X(float %x) {
+;
+; CHECK-SF-LABEL: faddRI_X:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 17792
+; CHECK-SF-NEXT: ori32 a0, a0, 2048
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fadds vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: faddRI_X:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 17792
+; CHECK-SF2-NEXT: ori32 a0, a0, 2048
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fadd = fadd float %x, 4097.0
+ ret float %fadd
+}
+
+define float @fsubRR(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fsubRR:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fsubs vr0, vr1, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fsubRR:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fsub.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fsub = fsub float %y, %x
+ ret float %fsub
+}
+
+define float @fsubRI(float %x) {
+;
+; CHECK-SF-LABEL: fsubRI:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fadds vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fsubRI:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fsub = fsub float %x, 10.0
+ ret float %fsub
+}
+
+define float @fsubRI_X(float %x) {
+;
+; CHECK-SF-LABEL: fsubRI_X:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 50560
+; CHECK-SF-NEXT: ori32 a0, a0, 2048
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fadds vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fsubRI_X:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 50560
+; CHECK-SF2-NEXT: ori32 a0, a0, 2048
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fadd.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fsub = fsub float %x, 4097.0
+ ret float %fsub
+}
+
+define float @fmulRR(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fmulRR:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fmuls vr0, vr1, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fmulRR:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fmul.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fmul = fmul float %y, %x
+ ret float %fmul
+}
+
+define float @fmulRI(float %x) {
+;
+; CHECK-SF-LABEL: fmulRI:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fmuls vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fmulRI:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fmul = fmul float %x, 10.0
+ ret float %fmul
+}
+
+define float @fmulRI_X(float %x) {
+;
+; CHECK-SF-LABEL: fmulRI_X:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 17792
+; CHECK-SF-NEXT: ori32 a0, a0, 2048
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fmuls vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fmulRI_X:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 17792
+; CHECK-SF2-NEXT: ori32 a0, a0, 2048
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fmul.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fmul = fmul float %x, 4097.0
+ ret float %fmul
+}
+
+define float @fdivRR(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fdivRR:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fdivs vr0, vr1, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fdivRR:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fdiv.32 vr0, vr1, vr0
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fdiv = fdiv float %y, %x
+ ret float %fdiv
+}
+
+define float @fdivRI(float %x) {
+;
+; CHECK-SF-LABEL: fdivRI:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fdivs vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fdivRI:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fdiv = fdiv float %x, 10.0
+ ret float %fdiv
+}
+
+define float @fdivRI_X(float %x) {
+;
+; CHECK-SF-LABEL: fdivRI_X:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 17792
+; CHECK-SF-NEXT: ori32 a0, a0, 2048
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fdivs vr0, vr0, vr1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fdivRI_X:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 17792
+; CHECK-SF2-NEXT: ori32 a0, a0, 2048
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fdiv.32 vr0, vr0, vr1
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fdiv = fdiv float %x, 4097.0
+ ret float %fdiv
+}
+
+define float @fnegRR(float %x) {
+;
+; CHECK-SF-LABEL: fnegRR:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fnegs vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fnegRR:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fneg.32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+
+entry:
+ %fneg = fneg float %x
+ ret float %fneg
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/br-d.ll b/llvm/test/CodeGen/CSKY/fpu/br-d.ll
new file mode 100644
index 0000000000000..9e7d804c0f642
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/br-d.ll
@@ -0,0 +1,2061 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
+
+;OEQ
+define i32 @brRR_oeq(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_oeq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB0_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB0_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_oeq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB0_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB0_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_oeq(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_oeq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI1_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB1_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB1_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI1_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_oeq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI1_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB1_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB1_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI1_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp oeq double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_oeq(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_oeq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI2_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB2_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB2_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI2_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_oeq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI2_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB2_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB2_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI2_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp oeq double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;NE
+define i32 @brRR_one(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_one:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a1
+; CHECK-DF-NEXT: or16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB3_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB3_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_one:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a1
+; CHECK-DF2-NEXT: or16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB3_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB3_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_one(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_one:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI4_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a1
+; CHECK-DF-NEXT: or16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB4_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB4_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI4_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_one:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI4_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a1
+; CHECK-DF2-NEXT: or16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB4_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB4_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI4_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp one double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_one(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_one:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a1
+; CHECK-DF-NEXT: or16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB5_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB5_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI5_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_one:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a1
+; CHECK-DF2-NEXT: or16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB5_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB5_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI5_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp one double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGT
+define i32 @brRR_ugt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ugt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB6_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB6_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ugt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB6_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB6_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ugt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ugt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB7_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB7_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI7_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ugt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB7_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB7_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI7_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ugt double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ugt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ugt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI8_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB8_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB8_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI8_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ugt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI8_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB8_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB8_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI8_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ugt double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGE
+define i32 @brRR_uge(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_uge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB9_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB9_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_uge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB9_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB9_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_uge(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_uge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI10_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB10_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB10_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI10_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_uge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI10_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB10_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB10_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI10_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp uge double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_uge(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_uge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI11_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB11_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB11_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI11_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_uge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI11_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB11_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB11_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI11_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp uge double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;ULT
+define i32 @brRR_ult(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ult:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB12_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB12_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ult:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB12_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB12_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ult(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ult:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI13_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB13_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB13_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI13_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ult:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI13_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB13_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB13_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI13_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ult double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ult(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ult:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI14_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB14_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB14_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI14_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ult:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI14_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB14_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB14_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI14_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ult double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;ULE
+define i32 @brRR_ule(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ule:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: bt32 .LBB15_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB15_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ule:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: bt32 .LBB15_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB15_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ule(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ule:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI16_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB16_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB16_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI16_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ule:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI16_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB16_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB16_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI16_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ule double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ule(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ule:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI17_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB17_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB17_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI17_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ule:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI17_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB17_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB17_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI17_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ule double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGT
+define i32 @brRR_ogt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ogt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB18_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB18_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ogt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB18_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB18_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ogt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ogt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI19_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB19_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB19_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI19_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ogt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI19_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB19_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB19_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI19_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ogt double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ogt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ogt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI20_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB20_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB20_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI20_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ogt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI20_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB20_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB20_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI20_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ogt double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGE
+define i32 @brRR_oge(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_oge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB21_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB21_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_oge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB21_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB21_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_oge(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_oge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI22_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB22_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB22_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI22_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_oge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI22_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB22_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB22_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI22_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp oge double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_oge(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_oge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI23_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB23_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB23_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI23_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_oge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI23_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB23_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB23_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI23_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp oge double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLT
+define i32 @brRR_olt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_olt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB24_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB24_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_olt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB24_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB24_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_olt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_olt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI25_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB25_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB25_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI25_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_olt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI25_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB25_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB25_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI25_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp olt double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_olt(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_olt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI26_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB26_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB26_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI26_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_olt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI26_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB26_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB26_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI26_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp olt double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLE
+define i32 @brRR_ole(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ole:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB27_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB27_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ole:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB27_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB27_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ole(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ole:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI28_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB28_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB28_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI28_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ole:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI28_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB28_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB28_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI28_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ole double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ole(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ole:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI29_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB29_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB29_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI29_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ole:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI29_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB29_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB29_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI29_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ole double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;False
+define i32 @brRR_false(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_false:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB30_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB30_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_false:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB30_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB30_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_false(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_false:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB31_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB31_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRI_false:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB31_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB31_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_false(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_false:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB32_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB32_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brR0_false:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB32_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB32_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;ORD
+define i32 @brRR_ord(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ord:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB33_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB33_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ord:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB33_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB33_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ord(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ord:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: bt32 .LBB34_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB34_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRI_ord:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: bt32 .LBB34_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB34_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ord(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ord:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: bt32 .LBB35_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB35_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brR0_ord:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: bt32 .LBB35_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB35_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;UEQ
+define i32 @brRR_ueq(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_ueq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvc32 a1
+; CHECK-DF-NEXT: and16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bf32 .LBB36_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB36_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_ueq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a1
+; CHECK-DF2-NEXT: and16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bf32 .LBB36_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB36_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ueq(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_ueq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI37_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvc32 a1
+; CHECK-DF-NEXT: and16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bf32 .LBB37_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB37_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI37_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_ueq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI37_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a1
+; CHECK-DF2-NEXT: and16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bf32 .LBB37_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB37_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI37_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp ueq double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ueq(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_ueq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI38_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvc32 a1
+; CHECK-DF-NEXT: and16 a0, a1
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bf32 .LBB38_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB38_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI38_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_ueq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI38_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a1
+; CHECK-DF2-NEXT: and16 a0, a1
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bf32 .LBB38_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB38_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI38_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ueq double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UNE
+define i32 @brRR_une(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_une:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: bf32 .LBB39_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB39_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_une:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: bf32 .LBB39_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB39_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_une(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_une:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI40_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: bf32 .LBB40_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB40_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI40_0:
+; CHECK-DF-NEXT: .quad 0x4024000000000000 # double 10
+;
+; CHECK-DF2-LABEL: brRI_une:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI40_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: bf32 .LBB40_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB40_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI40_0:
+; CHECK-DF2-NEXT: .quad 0x4024000000000000 # double 10
+entry:
+ %fcmp = fcmp une double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_une(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_une:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI41_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: bf32 .LBB41_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB41_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.3:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI41_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: brR0_une:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI41_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: bf32 .LBB41_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB41_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.3:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI41_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp une double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UNO
+define i32 @brRR_uno(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_uno:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: bt32 .LBB42_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB42_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_uno:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: bt32 .LBB42_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB42_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_uno(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_uno:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: bt32 .LBB43_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB43_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRI_uno:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: bt32 .LBB43_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB43_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_uno(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_uno:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: bt32 .LBB44_2
+; CHECK-DF-NEXT: # %bb.1: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB44_2: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brR0_uno:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: bt32 .LBB44_2
+; CHECK-DF2-NEXT: # %bb.1: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB44_2: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;True
+define i32 @brRR_true(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: brRR_true:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB45_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB45_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRR_true:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB45_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB45_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true double %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_true(double %x) {
+;
+;
+; CHECK-DF-LABEL: brRI_true:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB46_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB46_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brRI_true:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB46_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB46_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true double %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_true(double %x) {
+;
+;
+; CHECK-DF-LABEL: brR0_true:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: btsti32 a0, 0
+; CHECK-DF-NEXT: bt32 .LBB47_2
+; CHECK-DF-NEXT: # %bb.1: # %label1
+; CHECK-DF-NEXT: movi16 a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .LBB47_2: # %label2
+; CHECK-DF-NEXT: movi16 a0, 0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: brR0_true:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: btsti32 a0, 0
+; CHECK-DF2-NEXT: bt32 .LBB47_2
+; CHECK-DF2-NEXT: # %bb.1: # %label1
+; CHECK-DF2-NEXT: movi16 a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .LBB47_2: # %label2
+; CHECK-DF2-NEXT: movi16 a0, 0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true double %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/br-f.ll b/llvm/test/CodeGen/CSKY/fpu/br-f.ll
new file mode 100644
index 0000000000000..eb13f20187430
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/br-f.ll
@@ -0,0 +1,1751 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
+
+;OEQ
+define i32 @brRR_oeq(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB0_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB0_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB0_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB0_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_oeq(float %x) {
+;
+; CHECK-SF-LABEL: brRI_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: bt32 .LBB1_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB1_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: bt32 .LBB1_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB1_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_oeq(float %x) {
+;
+; CHECK-SF-LABEL: brR0_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: bt32 .LBB2_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB2_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: bt32 .LBB2_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB2_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;NE
+define i32 @brRR_one(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB3_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB3_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB3_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB3_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_one(float %x) {
+;
+; CHECK-SF-LABEL: brRI_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB4_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB4_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB4_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB4_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_one(float %x) {
+;
+; CHECK-SF-LABEL: brR0_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB5_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB5_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB5_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB5_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGT
+define i32 @brRR_ugt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: bt32 .LBB6_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB6_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: bt32 .LBB6_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB6_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ugt(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB7_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB7_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB7_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB7_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ugt(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: bt32 .LBB8_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB8_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplsz.32 vr0
+; CHECK-SF2-NEXT: bt32 .LBB8_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB8_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UGE
+define i32 @brRR_uge(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB9_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB9_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB9_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB9_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_uge(float %x) {
+;
+; CHECK-SF-LABEL: brRI_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: bt32 .LBB10_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB10_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: bt32 .LBB10_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB10_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_uge(float %x) {
+;
+; CHECK-SF-LABEL: brR0_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: bf32 .LBB11_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB11_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpltz.32 vr0
+; CHECK-SF2-NEXT: bt32 .LBB11_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB11_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;ULT
+define i32 @brRR_ult(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB12_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB12_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB12_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB12_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ult(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: bt32 .LBB13_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB13_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: bt32 .LBB13_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB13_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ult(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: bt32 .LBB14_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB14_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphsz.32 vr0
+; CHECK-SF2-NEXT: bt32 .LBB14_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB14_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;ULE
+define i32 @brRR_ule(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: bt32 .LBB15_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB15_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: bt32 .LBB15_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB15_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ule(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB16_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB16_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB16_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB16_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ule(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: bf32 .LBB17_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB17_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphz.32 vr0
+; CHECK-SF2-NEXT: bt32 .LBB17_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB17_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGT
+define i32 @brRR_ogt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB18_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB18_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB18_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB18_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ogt(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB19_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB19_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB19_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB19_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ogt(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB20_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB20_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB20_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB20_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SGE
+define i32 @brRR_oge(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB21_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB21_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB21_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB21_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_oge(float %x) {
+;
+; CHECK-SF-LABEL: brRI_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB22_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB22_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB22_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB22_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_oge(float %x) {
+;
+; CHECK-SF-LABEL: brR0_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB23_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB23_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB23_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB23_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLT
+define i32 @brRR_olt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB24_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB24_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB24_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB24_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_olt(float %x) {
+;
+; CHECK-SF-LABEL: brRI_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB25_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB25_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB25_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB25_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_olt(float %x) {
+;
+; CHECK-SF-LABEL: brR0_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB26_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB26_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpltz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB26_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB26_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;SLE
+define i32 @brRR_ole(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB27_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB27_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB27_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB27_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ole(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB28_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB28_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB28_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB28_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ole(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB29_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB29_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB29_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB29_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;False
+define i32 @brRR_false(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_false:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB30_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB30_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_false:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB30_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB30_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_false(float %x) {
+;
+; CHECK-SF-LABEL: brRI_false:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB31_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB31_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_false:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB31_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB31_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_false(float %x) {
+;
+; CHECK-SF-LABEL: brR0_false:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB32_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB32_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_false:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB32_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB32_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp false float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;ORD
+define i32 @brRR_ord(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB33_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB33_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB33_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB33_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ord(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: bt32 .LBB34_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB34_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: bt32 .LBB34_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB34_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ord(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: bt32 .LBB35_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB35_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: bt32 .LBB35_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB35_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+
+;UEQ
+define i32 @brRR_ueq(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bf32 .LBB36_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB36_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bf32 .LBB36_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB36_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_ueq(float %x) {
+;
+; CHECK-SF-LABEL: brRI_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bf32 .LBB37_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB37_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bf32 .LBB37_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB37_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_ueq(float %x) {
+;
+; CHECK-SF-LABEL: brR0_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bf32 .LBB38_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB38_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bf32 .LBB38_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB38_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UNE
+define i32 @brRR_une(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: bf32 .LBB39_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB39_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: bf32 .LBB39_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB39_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_une(float %x) {
+;
+; CHECK-SF-LABEL: brRI_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 16672
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: bf32 .LBB40_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB40_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 16672
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: bf32 .LBB40_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB40_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_une(float %x) {
+;
+; CHECK-SF-LABEL: brR0_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: bf32 .LBB41_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB41_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: bf32 .LBB41_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB41_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;UNO
+define i32 @brRR_uno(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: bt32 .LBB42_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB42_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: bt32 .LBB42_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB42_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_uno(float %x) {
+;
+; CHECK-SF-LABEL: brRI_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: bt32 .LBB43_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB43_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: bt32 .LBB43_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB43_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_uno(float %x) {
+;
+; CHECK-SF-LABEL: brR0_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: bt32 .LBB44_2
+; CHECK-SF-NEXT: # %bb.1: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB44_2: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: bt32 .LBB44_2
+; CHECK-SF2-NEXT: # %bb.1: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB44_2: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+;True
+define i32 @brRR_true(float %x, float %y) {
+;
+; CHECK-SF-LABEL: brRR_true:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB45_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB45_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRR_true:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB45_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB45_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true float %y, %x
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brRI_true(float %x) {
+;
+; CHECK-SF-LABEL: brRI_true:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB46_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB46_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brRI_true:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB46_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB46_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true float %x, 10.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
+
+define i32 @brR0_true(float %x) {
+;
+; CHECK-SF-LABEL: brR0_true:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: btsti32 a0, 0
+; CHECK-SF-NEXT: bt32 .LBB47_2
+; CHECK-SF-NEXT: # %bb.1: # %label1
+; CHECK-SF-NEXT: movi16 a0, 1
+; CHECK-SF-NEXT: rts16
+; CHECK-SF-NEXT: .LBB47_2: # %label2
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: brR0_true:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: btsti32 a0, 0
+; CHECK-SF2-NEXT: bt32 .LBB47_2
+; CHECK-SF2-NEXT: # %bb.1: # %label1
+; CHECK-SF2-NEXT: movi16 a0, 1
+; CHECK-SF2-NEXT: rts16
+; CHECK-SF2-NEXT: .LBB47_2: # %label2
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp true float %x, 0.0
+ br i1 %fcmp, label %label1, label %label2
+label1:
+ ret i32 1
+label2:
+ ret i32 0
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/cmp-d.ll b/llvm/test/CodeGen/CSKY/fpu/cmp-d.ll
new file mode 100644
index 0000000000000..af9bddda994b4
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/cmp-d.ll
@@ -0,0 +1,766 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
+
+
+;ueq
+
+define i1 @FCMP_DOUBLE_ueq(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ueq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a1
+; CHECK-DF-NEXT: or16 a0, a1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ueq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a1
+; CHECK-DF2-NEXT: or16 a0, a1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ueq(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ueq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI1_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a1
+; CHECK-DF-NEXT: or16 a0, a1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI1_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ueq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI1_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a1
+; CHECK-DF2-NEXT: or16 a0, a1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI1_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ueq double %x, 0.0
+ ret i1 %fcmp
+}
+
+;une
+
+define i1 @FCMP_DOUBLE_une(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_une:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_une:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_une(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_une:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI3_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI3_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_une:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI3_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI3_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp une double %x, 0.0
+ ret i1 %fcmp
+}
+
+;ugt
+
+define i1 @FCMP_DOUBLE_ugt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ugt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ugt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ugt(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ugt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI5_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI5_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ugt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI5_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI5_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ugt double %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;uge
+
+define i1 @FCMP_DOUBLE_uge(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_uge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_uge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_uge(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_uge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI7_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI7_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_uge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI7_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI7_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp uge double %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ult
+
+define i1 @FCMP_DOUBLE_ult(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ult:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ult:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ult(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ult:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI9_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI9_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ult:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI9_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI9_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ult double %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ule
+
+define i1 @FCMP_DOUBLE_ule(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ule:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ule:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ule(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ule:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI11_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: xori32 a0, a0, 1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI11_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ule:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI11_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: xori32 a0, a0, 1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI11_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ule double %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ogt
+
+define i1 @FCMP_DOUBLE_ogt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ogt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ogt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ogt(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ogt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI13_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI13_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ogt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI13_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI13_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ogt double %x, 0.0
+ ret i1 %fcmp
+}
+
+;oge
+
+define i1 @FCMP_DOUBLE_oge(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_oge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_oge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_oge(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_oge:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI15_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI15_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_oge:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI15_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI15_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp oge double %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;olt
+
+define i1 @FCMP_DOUBLE_olt(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_olt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpltd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_olt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_olt(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_olt:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI17_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpltd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI17_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_olt:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI17_0]
+; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI17_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp olt double %x, 0.0
+ ret i1 %fcmp
+}
+
+;ole
+
+define i1 @FCMP_DOUBLE_ole(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ole:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmphsd vr0, vr1
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ole:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ole(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ole:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI19_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmphsd vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI19_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ole:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI19_0]
+; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI19_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp ole double %x, 0.0
+ ret i1 %fcmp
+}
+
+;one
+
+define i1 @FCMP_DOUBLE_one(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_one:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvc32 a1
+; CHECK-DF-NEXT: and16 a0, a1
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_one:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a1
+; CHECK-DF2-NEXT: and16 a0, a1
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_one(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_one:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI21_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpuod vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvc32 a1
+; CHECK-DF-NEXT: and16 a0, a1
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI21_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_one:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI21_0]
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvc32 a1
+; CHECK-DF2-NEXT: and16 a0, a1
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI21_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp one double %x, 0.0
+ ret i1 %fcmp
+}
+
+;oeq
+
+define i1 @FCMP_DOUBLE_oeq(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_oeq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpned vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_oeq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_oeq(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_oeq:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: grs32 a0, .LCPI23_0
+; CHECK-DF-NEXT: fldd vr1, (a0, 0)
+; CHECK-DF-NEXT: fcmpned vr0, vr1
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI23_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_oeq:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: flrw.64 vr1, [.LCPI23_0]
+; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI23_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %fcmp = fcmp oeq double %x, 0.0
+ ret i1 %fcmp
+}
+
+;ord
+
+define i1 @FCMP_DOUBLE_ord(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_ord:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_ord:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_ord(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_ord:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: mvcv16 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_ord:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: mvcv16 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord double %x, 0.0
+ ret i1 %fcmp
+}
+
+;uno
+
+define i1 @FCMP_DOUBLE_uno(double %x, double %y) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_uno:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr1, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_uno:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr1, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno double %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @FCMP_DOUBLE_I_uno(double %x) {
+;
+;
+; CHECK-DF-LABEL: FCMP_DOUBLE_I_uno:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fcmpuod vr0, vr0
+; CHECK-DF-NEXT: mvc32 a0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: FCMP_DOUBLE_I_uno:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fcmpuo.64 vr0, vr0
+; CHECK-DF2-NEXT: mvc32 a0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno double %x, 0.0
+ ret i1 %fcmp
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/cmp-f.ll b/llvm/test/CodeGen/CSKY/fpu/cmp-f.ll
new file mode 100644
index 0000000000000..2bb5534c422ce
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/cmp-f.ll
@@ -0,0 +1,896 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
+
+;ueq
+define i1 @fcmpRR_ueq(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ueq(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ueq(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ueq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: or16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ueq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: or16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ueq float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;une
+define i1 @fcmpRR_une(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_une(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_une(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_une:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_une:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp une float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ugt
+define i1 @fcmpRR_ugt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ugt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ugt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ugt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ugt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ugt float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;uge
+define i1 @fcmpRR_uge(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_uge(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_uge(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_uge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_uge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpltz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uge float %x, 0.0
+ ret i1 %fcmp
+}
+
+;ult
+define i1 @fcmpRR_ult(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ult(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ult(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ult:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ult:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ult float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ule
+define i1 @fcmpRR_ule(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ule(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ule(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ule:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: xori32 a0, a0, 1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ule:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: xori32 a0, a0, 1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ule float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ogt
+define i1 @fcmpRR_ogt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ogt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ogt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ogt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ogt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ogt float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;oge
+define i1 @fcmpRR_oge(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_oge(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_oge(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_oge:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_oge:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oge float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;olt
+define i1 @fcmpRR_olt(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmplts vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_olt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmplts vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_olt(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_olt:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzhss vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_olt:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpltz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp olt float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ole
+define i1 @fcmpRR_ole(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmphss vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ole(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmphss vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ole(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ole:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpzlss vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ole:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmplsz.32 vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ole float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;one
+define i1 @fcmpRR_one(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_one(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_one(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_one:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvc32 a1
+; CHECK-SF-NEXT: and16 a0, a1
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_one:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a1
+; CHECK-SF2-NEXT: and16 a0, a1
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp one float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;oeq
+define i1 @fcmpRR_oeq(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpnes vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_oeq(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: movih32 a0, 49440
+; CHECK-SF-NEXT: fmtvrl vr1, a0
+; CHECK-SF-NEXT: fcmpnes vr0, vr1
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: movih32 a0, 49440
+; CHECK-SF2-NEXT: fmtvr.32.1 vr1, a0
+; CHECK-SF2-NEXT: fcmpne.32 vr0, vr1
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_oeq(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_oeq:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpznes vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_oeq:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpnez.32 vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp oeq float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;ord
+define i1 @fcmpRR_ord(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_ord(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_ord(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_ord:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvcv16 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_ord:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvcv16 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp ord float %x, 0.0
+ ret i1 %fcmp
+}
+
+
+;uno
+define i1 @fcmpRR_uno(float %x, float %y) {
+;
+; CHECK-SF-LABEL: fcmpRR_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr1, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRR_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr1, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %y, %x
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_uno(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %x, -10.0
+ ret i1 %fcmp
+}
+
+define i1 @fcmpRI_X_uno(float %x) {
+;
+; CHECK-SF-LABEL: fcmpRI_X_uno:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fcmpuos vr0, vr0
+; CHECK-SF-NEXT: mvc32 a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fcmpRI_X_uno:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
+; CHECK-SF2-NEXT: mvc32 a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fcmp = fcmp uno float %x, 0.0
+ ret i1 %fcmp
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/cvt-d.ll b/llvm/test/CodeGen/CSKY/fpu/cvt-d.ll
new file mode 100644
index 0000000000000..1bdb4f8784ebe
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/cvt-d.ll
@@ -0,0 +1,371 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
+
+
+; double --> float
+define float @fptruncR_double_0(double %x) {
+;
+; CHECK-DF-LABEL: fptruncR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtos vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptruncR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fdtos vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptrunc = fptrunc double %x to float
+ ret float %fptrunc
+}
+
+define double @fpextR_double_0(float %x) {
+;
+; CHECK-DF-LABEL: fpextR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fstod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fpextR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fstod vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fpext = fpext float %x to double
+ ret double %fpext
+}
+
+; double --> i32
+define i32 @fptosiR_double_1(double %x) {
+;
+;
+; CHECK-DF-LABEL: fptosiR_double_1:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtosi.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptosiR_double_1:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.s32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptosi = fptosi double %x to i32
+ ret i32 %fptosi
+}
+
+
+; double --> i16
+define i16 @fptosiR_double_2(double %x) {
+;
+;
+; CHECK-DF-LABEL: fptosiR_double_2:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtosi.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptosiR_double_2:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.s32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptosi = fptosi double %x to i16
+ ret i16 %fptosi
+}
+
+
+; double --> i8
+define i8 @fptosiR_double_3(double %x) {
+;
+;
+; CHECK-DF-LABEL: fptosiR_double_3:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtosi.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptosiR_double_3:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.s32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptosi = fptosi double %x to i8
+ ret i8 %fptosi
+}
+
+; double --> i1
+define i1 @fptosiR_double_4(double %x) {
+;
+;
+; CHECK-DF-LABEL: fptosiR_double_4:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtosi.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptosiR_double_4:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.s32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptosi = fptosi double %x to i1
+ ret i1 %fptosi
+}
+
+; double --> i32
+define i32 @fptouiR_double_1(double %x) {
+;
+; CHECK-DF-LABEL: fptouiR_double_1:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtoui.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptouiR_double_1:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.u32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+
+entry:
+ %fptoui = fptoui double %x to i32
+ ret i32 %fptoui
+}
+
+
+; double --> i16
+define i16 @fptouiR_double_2(double %x) {
+;
+; CHECK-DF-LABEL: fptouiR_double_2:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtoui.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptouiR_double_2:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.u32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+
+entry:
+ %fptoui = fptoui double %x to i16
+ ret i16 %fptoui
+}
+
+
+; double --> i8
+define i8 @fptouiR_double_3(double %x) {
+;
+; CHECK-DF-LABEL: fptouiR_double_3:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtoui.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptouiR_double_3:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.u32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptoui = fptoui double %x to i8
+ ret i8 %fptoui
+}
+
+
+; double --> i1
+define i1 @fptouiR_double_4(double %x) {
+;
+;
+; CHECK-DF-LABEL: fptouiR_double_4:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fdtoui.rz vr0, vr0
+; CHECK-DF-NEXT: fmfvrl a0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: fptouiR_double_4:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fftoi.f64.u32.rz vr0, vr0
+; CHECK-DF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %fptoui = fptoui double %x to i1
+ ret i1 %fptoui
+}
+
+
+; i32/i16/i8/i1 --> double
+
+define double @sitofpR_double_0(i32 %x) {
+;
+;
+; CHECK-DF-LABEL: sitofpR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fsitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: sitofpR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.s32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i32 %x to double
+ ret double %sitofp
+}
+
+define double @sitofpR_double_1(i16 %x) {
+;
+;
+; CHECK-DF-LABEL: sitofpR_double_1:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: sexth16 a0, a0
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fsitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: sitofpR_double_1:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: sexth16 a0, a0
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.s32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i16 %x to double
+ ret double %sitofp
+}
+
+define double @sitofpR_double_2(i8 %x) {
+;
+;
+; CHECK-DF-LABEL: sitofpR_double_2:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: sextb16 a0, a0
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fsitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: sitofpR_double_2:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: sextb16 a0, a0
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.s32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i8 %x to double
+ ret double %sitofp
+}
+
+define double @sitofpR_double_3(i1 %x) {
+;
+;
+; CHECK-DF-LABEL: sitofpR_double_3:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: sext32 a0, a0, 0, 0
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fsitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: sitofpR_double_3:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: sext32 a0, a0, 0, 0
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.s32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i1 %x to double
+ ret double %sitofp
+}
+
+; i32/i16/i8/i1 --> double
+
+define double @uitofpR_double_0(i32 %x) {
+;
+;
+; CHECK-DF-LABEL: uitofpR_double_0:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fuitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: uitofpR_double_0:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.u32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i32 %x to double
+ ret double %uitofp
+}
+
+define double @uitofpR_double_1(i16 %x) {
+;
+;
+; CHECK-DF-LABEL: uitofpR_double_1:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: zexth16 a0, a0
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fuitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: uitofpR_double_1:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: zexth16 a0, a0
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.u32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i16 %x to double
+ ret double %uitofp
+}
+
+define double @uitofpR_double_2(i8 %x) {
+;
+;
+; CHECK-DF-LABEL: uitofpR_double_2:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: zextb16 a0, a0
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fuitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: uitofpR_double_2:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: zextb16 a0, a0
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.u32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i8 %x to double
+ ret double %uitofp
+}
+
+define double @uitofpR_double_3(i1 %x) {
+;
+;
+; CHECK-DF-LABEL: uitofpR_double_3:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: andi32 a0, a0, 1
+; CHECK-DF-NEXT: fmtvrl vr0, a0
+; CHECK-DF-NEXT: fuitod vr0, vr0
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: uitofpR_double_3:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: andi32 a0, a0, 1
+; CHECK-DF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-DF2-NEXT: fitof.u32.f64 vr0, vr0
+; CHECK-DF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i1 %x to double
+ ret double %uitofp
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/cvt-f.ll b/llvm/test/CodeGen/CSKY/fpu/cvt-f.ll
new file mode 100644
index 0000000000000..07055fe0d4d0d
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/cvt-f.ll
@@ -0,0 +1,334 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
+
+
+; float --> i32
+define i32 @fptosiR_float_1(float %x) {
+;
+; CHECK-SF-LABEL: fptosiR_float_1:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstosi.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptosiR_float_1:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fptosi = fptosi float %x to i32
+ ret i32 %fptosi
+}
+
+
+; float --> i16
+define i16 @fptosiR_float_2(float %x) {
+;
+; CHECK-SF-LABEL: fptosiR_float_2:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstosi.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptosiR_float_2:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fptosi = fptosi float %x to i16
+ ret i16 %fptosi
+}
+
+
+; float --> i8
+define i8 @fptosiR_float_3(float %x) {
+;
+; CHECK-SF-LABEL: fptosiR_float_3:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstosi.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptosiR_float_3:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fptosi = fptosi float %x to i8
+ ret i8 %fptosi
+}
+
+
+; float --> i1
+define i1 @fptosiR_float_4(float %x) {
+;
+; CHECK-SF-LABEL: fptosiR_float_4:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstosi.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptosiR_float_4:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.s32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fptosi = fptosi float %x to i1
+ ret i1 %fptosi
+}
+
+
+
+
+; float --> i32
+define i32 @fptouiR_float_1(float %x) {
+;
+; CHECK-SF-LABEL: fptouiR_float_1:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstoui.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptouiR_float_1:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fptoui = fptoui float %x to i32
+ ret i32 %fptoui
+}
+
+
+
+; float --> i16
+define i16 @fptouiR_float_2(float %x) {
+;
+; CHECK-SF-LABEL: fptouiR_float_2:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstoui.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptouiR_float_2:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fptoui = fptoui float %x to i16
+ ret i16 %fptoui
+}
+
+
+
+; float --> i8
+define i8 @fptouiR_float_3(float %x) {
+;
+; CHECK-SF-LABEL: fptouiR_float_3:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstoui.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptouiR_float_3:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+
+
+entry:
+ %fptoui = fptoui float %x to i8
+ ret i8 %fptoui
+}
+
+
+; float --> i1
+define i1 @fptouiR_float_4(float %x) {
+;
+; CHECK-SF-LABEL: fptouiR_float_4:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstoui.rz vr0, vr0
+; CHECK-SF-NEXT: fmfvrl a0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: fptouiR_float_4:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fftoi.f32.u32.rz vr0, vr0
+; CHECK-SF2-NEXT: fmfvr.32.1 a0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %fptoui = fptoui float %x to i1
+ ret i1 %fptoui
+}
+
+; i32/i16/i8/i1 --> float
+
+define float @sitofpR_float_0(i32 %x) {
+;
+; CHECK-SF-LABEL: sitofpR_float_0:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fsitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: sitofpR_float_0:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i32 %x to float
+ ret float %sitofp
+}
+
+define float @sitofpR_float_1(i16 %x) {
+;
+; CHECK-SF-LABEL: sitofpR_float_1:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: sexth16 a0, a0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fsitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: sitofpR_float_1:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: sexth16 a0, a0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i16 %x to float
+ ret float %sitofp
+}
+
+define float @sitofpR_float_2(i8 %x) {
+;
+; CHECK-SF-LABEL: sitofpR_float_2:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: sextb16 a0, a0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fsitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: sitofpR_float_2:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: sextb16 a0, a0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i8 %x to float
+ ret float %sitofp
+}
+
+define float @sitofpR_float_3(i1 %x) {
+;
+; CHECK-SF-LABEL: sitofpR_float_3:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: sext32 a0, a0, 0, 0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fsitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: sitofpR_float_3:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: sext32 a0, a0, 0, 0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.s32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %sitofp = sitofp i1 %x to float
+ ret float %sitofp
+}
+
+; i32/i16/i8/i1 --> float
+
+define float @uitofpR_float_0(i32 %x) {
+;
+; CHECK-SF-LABEL: uitofpR_float_0:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fuitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: uitofpR_float_0:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i32 %x to float
+ ret float %uitofp
+}
+
+define float @uitofpR_float_1(i16 %x) {
+;
+; CHECK-SF-LABEL: uitofpR_float_1:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: zexth16 a0, a0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fuitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: uitofpR_float_1:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: zexth16 a0, a0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i16 %x to float
+ ret float %uitofp
+}
+
+define float @uitofpR_float_2(i8 %x) {
+;
+; CHECK-SF-LABEL: uitofpR_float_2:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: zextb16 a0, a0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fuitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: uitofpR_float_2:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: zextb16 a0, a0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i8 %x to float
+ ret float %uitofp
+}
+
+define float @uitofpR_float_3(i1 %x) {
+;
+; CHECK-SF-LABEL: uitofpR_float_3:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: andi32 a0, a0, 1
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: fuitos vr0, vr0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: uitofpR_float_3:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: andi32 a0, a0, 1
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: fitof.u32.f32 vr0, vr0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %uitofp = uitofp i1 %x to float
+ ret float %uitofp
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll
new file mode 100644
index 0000000000000..e31fd409d2775
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll
@@ -0,0 +1,106 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2
+
+define double @load_I_d(double* nocapture readonly %a) local_unnamed_addr #0 {
+;
+;
+; CHECK-DF-LABEL: load_I_d:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fldd vr0, (a0, 24)
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: load_I_d:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fld.64 vr0, (a0, 24)
+; CHECK-DF2-NEXT: rts16
+entry:
+ %arrayidx = getelementptr inbounds double, double* %a, i64 3
+ %0 = load double, double* %arrayidx, align 4
+ ret double %0
+}
+
+
+
+define double @load_R_d(double* nocapture readonly %a, i32 %b) local_unnamed_addr #0 {
+;
+;
+; CHECK-DF-LABEL: load_R_d:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fldrd vr0, (a0, a1 << 3)
+; CHECK-DF-NEXT: rts16
+;
+; CHECK-DF2-LABEL: load_R_d:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fldr.64 vr0, (a0, a1 << 3)
+; CHECK-DF2-NEXT: rts16
+entry:
+ %idxprom = sext i32 %b to i64
+ %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom
+ %0 = load double, double* %arrayidx, align 4
+ ret double %0
+}
+
+define double @store_I_d(double* %a, double %b) local_unnamed_addr #0 {
+;
+;
+; CHECK-DF-LABEL: store_I_d:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fstd vr0, (a0, 24)
+; CHECK-DF-NEXT: grs32 a0, .LCPI2_0
+; CHECK-DF-NEXT: fldd vr0, (a0, 0)
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI2_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: store_I_d:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fst.64 vr0, (a0, 24)
+; CHECK-DF2-NEXT: flrw.64 vr0, [.LCPI2_0]
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI2_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %arrayidx = getelementptr inbounds double, double* %a, i64 3
+ store double %b, double* %arrayidx, align 4
+ ret double 0.0
+}
+
+define double @store_R_d(double* %a, i32 %b, double %c) local_unnamed_addr #0 {
+;
+;
+; CHECK-DF-LABEL: store_R_d:
+; CHECK-DF: # %bb.0: # %entry
+; CHECK-DF-NEXT: fstrd vr0, (a0, a1 << 3)
+; CHECK-DF-NEXT: grs32 a0, .LCPI3_0
+; CHECK-DF-NEXT: fldd vr0, (a0, 0)
+; CHECK-DF-NEXT: rts16
+; CHECK-DF-NEXT: .p2align 1
+; CHECK-DF-NEXT: # %bb.1:
+; CHECK-DF-NEXT: .p2align 2
+; CHECK-DF-NEXT: .LCPI3_0:
+; CHECK-DF-NEXT: .quad 0x0000000000000000 # double 0
+;
+; CHECK-DF2-LABEL: store_R_d:
+; CHECK-DF2: # %bb.0: # %entry
+; CHECK-DF2-NEXT: fstr.64 vr0, (a0, a1 << 3)
+; CHECK-DF2-NEXT: flrw.64 vr0, [.LCPI3_0]
+; CHECK-DF2-NEXT: rts16
+; CHECK-DF2-NEXT: .p2align 1
+; CHECK-DF2-NEXT: # %bb.1:
+; CHECK-DF2-NEXT: .p2align 2
+; CHECK-DF2-NEXT: .LCPI3_0:
+; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0
+entry:
+ %idxprom = sext i32 %b to i64
+ %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom
+ store double %c, double* %arrayidx, align 4
+ ret double 0.0
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll
new file mode 100644
index 0000000000000..bbcde8e6430a9
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll
@@ -0,0 +1,83 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF
+; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2
+
+define float @load_I_w(float* nocapture readonly %a) local_unnamed_addr #0 {
+;
+; CHECK-SF-LABEL: load_I_w:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: flds vr0, (a0, 12)
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: load_I_w:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fld.32 vr0, (a0, 12)
+; CHECK-SF2-NEXT: rts16
+entry:
+ %arrayidx = getelementptr inbounds float, float* %a, i64 3
+ %0 = load float, float* %arrayidx, align 4
+ ret float %0
+}
+
+define float @load_R_w(float* nocapture readonly %a, i32 %b) local_unnamed_addr #0 {
+;
+; CHECK-SF-LABEL: load_R_w:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fldrs vr0, (a0, a1 << 2)
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: load_R_w:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fldr.32 vr0, (a0, a1 << 2)
+; CHECK-SF2-NEXT: rts16
+entry:
+ %idxprom = sext i32 %b to i64
+ %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
+ %0 = load float, float* %arrayidx, align 4
+ ret float %0
+}
+
+
+define float @store_I_w(float* %a, float %b) local_unnamed_addr #0 {
+;
+; CHECK-SF-LABEL: store_I_w:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fsts vr0, (a0, 12)
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: store_I_w:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fst.32 vr0, (a0, 12)
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %arrayidx = getelementptr inbounds float, float* %a, i64 3
+ store float %b, float* %arrayidx, align 4
+ ret float 0.0
+}
+
+define float @store_R_w(float* %a, i32 %b, float %c) local_unnamed_addr #0 {
+;
+; CHECK-SF-LABEL: store_R_w:
+; CHECK-SF: # %bb.0: # %entry
+; CHECK-SF-NEXT: fstrs vr0, (a0, a1 << 2)
+; CHECK-SF-NEXT: movi16 a0, 0
+; CHECK-SF-NEXT: fmtvrl vr0, a0
+; CHECK-SF-NEXT: rts16
+;
+; CHECK-SF2-LABEL: store_R_w:
+; CHECK-SF2: # %bb.0: # %entry
+; CHECK-SF2-NEXT: fstr.32 vr0, (a0, a1 << 2)
+; CHECK-SF2-NEXT: movi16 a0, 0
+; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0
+; CHECK-SF2-NEXT: rts16
+entry:
+ %idxprom = sext i32 %b to i64
+ %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom
+ store float %c, float* %arrayidx, align 4
+ ret float 0.0
+}
diff --git a/llvm/test/CodeGen/CSKY/fpu/lit.local.cfg b/llvm/test/CodeGen/CSKY/fpu/lit.local.cfg
new file mode 100644
index 0000000000000..37335bd736850
--- /dev/null
+++ b/llvm/test/CodeGen/CSKY/fpu/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'CSKY' in config.root.targets:
+ config.unsupported = True
diff --git a/llvm/test/MC/CSKY/fpuv2.s b/llvm/test/MC/CSKY/fpuv2.s
new file mode 100644
index 0000000000000..7d4e7a4682bec
--- /dev/null
+++ b/llvm/test/MC/CSKY/fpuv2.s
@@ -0,0 +1,31 @@
+# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+fpuv2_sf -mattr=+fpuv2_df \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fldms vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x30]
+fldms vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fldmd vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x31]
+fldmd vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fstms vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x34]
+fstms vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fstmd vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x35]
+fstmd vr1-vr2, (a1)
+
+# RUN: not llvm-mc -triple csky -mattr=+fpuv2_sf -mattr=+fpuv2_df --defsym=ERR=1 < %s 2>&1 | FileCheck %s
+
+.ifdef ERR
+fldms vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
+fldms vr1-vr31, (a1) # CHECK: :[[#@LINE]]:8: error: Register sequence is not valid
+fstms vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
+fstms vr1-vr31, (a1) # CHECK: :[[#@LINE]]:8: error: Register sequence is not valid
+fldmd vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
+fldmd vr1-vr31, (a1) # CHECK: :[[#@LINE]]:8: error: Register sequence is not valid
+fstmd vr1-vr33, (a1) # CHECK: :[[#@LINE]]:12: error: invalid register
+fstmd vr1-vr31, (a1) # CHECK: :[[#@LINE]]:8: error: Register sequence is not valid
+.endif
diff --git a/llvm/test/MC/CSKY/fpuv3.s b/llvm/test/MC/CSKY/fpuv3.s
new file mode 100644
index 0000000000000..071ad10cfbe43
--- /dev/null
+++ b/llvm/test/MC/CSKY/fpuv3.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc %s -triple=csky -show-encoding -csky-no-aliases -mattr=+fpuv3_sf,+fpuv3_df \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: fldm.32 vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x30]
+fldm.32 vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fldm.64 vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x31]
+fldm.64 vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fstm.32 vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x34]
+fstm.32 vr1-vr2, (a1)
+
+# CHECK-ASM-AND-OBJ: fstm.64 vr1-vr2, (a1)
+# CHECK-ASM: encoding: [0x21,0xf4,0x01,0x35]
+fstm.64 vr1-vr2, (a1)
+
+# RUN: not llvm-mc -triple csky -mattr=+fpuv3_sf -mattr=+fpuv3_df --defsym=ERR=1 < %s 2>&1 | FileCheck %s
+
+.ifdef ERR
+fstm.32 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
+fstm.64 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
+fldm.32 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
+fldm.64 vr1-vr33, (a1) # CHECK: :[[#@LINE]]:14: error: invalid register
+.endif
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