[PATCH] D118222: [RISCV] Split f64 undef into two i32 undefs
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 26 22:01:06 PST 2022
pcwang-thead updated this revision to Diff 403499.
pcwang-thead added a comment.
Move test to `double-calling-conv.ll`.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118222/new/
https://reviews.llvm.org/D118222
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/double-calling-conv.ll
Index: llvm/test/CodeGen/RISCV/double-calling-conv.ll
===================================================================
--- llvm/test/CodeGen/RISCV/double-calling-conv.ll
+++ llvm/test/CodeGen/RISCV/double-calling-conv.ll
@@ -142,3 +142,10 @@
%1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
ret double %1
}
+
+define double @func_return_double_undef() nounwind {
+; RV32IFD-LABEL: func_return_double_undef:
+; RV32IFD: # %bb.0:
+; RV32IFD-NEXT: ret
+ ret double undef
+}
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7510,6 +7510,12 @@
if (Op0->getOpcode() == RISCVISD::BuildPairF64)
return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
+ if (Op0->isUndef()) {
+ SDValue Lo = DAG.getUNDEF(MVT::i32);
+ SDValue Hi = DAG.getUNDEF(MVT::i32);
+ return DCI.CombineTo(N, Lo, Hi);
+ }
+
SDLoc DL(N);
// It's cheaper to materialise two 32-bit integers than to load a double
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