[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd

[Matt Devereau via Phabricator via llvm-commits]

MattDevereau marked an inline comment as done.
MattDevereau added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:168
 def SDT_AArch64Arith : SDTypeProfile<1, 3, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
+  SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2>, SDTCisSameAs<2,3>, SDTCisSameNumEltsAs<0,1>
----------------
paulwalker-arm wrote:
> Out of interest are the `SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>` bits removable? I'm thinking they're redundant given the next line is now very specific about what the types of those operands are.
Removing them has no effect on the tests added in this patch or anything in the `check-llvm` target


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117689/new/

https://reviews.llvm.org/D117689