[PATCH] D117689: [AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:168
 def SDT_AArch64Arith : SDTypeProfile<1, 3, [
   SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
+  SDTCVecEltisVT<1,i1>, SDTCisSameAs<0,2>, SDTCisSameAs<2,3>, SDTCisSameNumEltsAs<0,1>
----------------
Out of interest are the `SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>` bits removable? I'm thinking they're redundant given the next line is now very specific about what the types of those operands are.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:243
 
+def FMUL_ZPmZ_patfrags : PatFrags<(ops node:$Pg, node:$Op1, node:$Op2), [
+  (int_aarch64_sve_fmul node:$Pg, node:$Op1, node:$Op2),
----------------
We already have a defined naming scheme for these operations, so these should be named `AArch64fadd_m1, AArch64fmul_m1 & AArch64fsub_m1`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D117689/new/

https://reviews.llvm.org/D117689