[PATCH] D118233: [MachineVerifier] Report allocatable classes for physical register copies

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, arsenm.
Herald added subscribers: luke957, luismarques, simoncook, s.egerton, PkmX, hiraditya.
lewis-revill requested review of this revision.
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The method getMinimalPhysRegClassLLT is used by the machine verifier on gMIR to find the register class for a physical register operand of a copy to/from a physical register. It then uses the register class to determine the size of the register to verify that the copy has matching sizes.

If this method can report unallocatable register classes as the best match for a physical register then we can run into the issue where, since unallocatable register classes are used as dummy classes where the type/size is unknown (IE for RISC-V), then the reported size doesn't match that of the register class that the register actually belongs to.

This may not be the only/neatest way of solving this issue but the issue is a blocker for RISC-V GlobalISel support.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118233

Files:
  llvm/lib/CodeGen/TargetRegisterInfo.cpp


Index: llvm/lib/CodeGen/TargetRegisterInfo.cpp
===================================================================
--- llvm/lib/CodeGen/TargetRegisterInfo.cpp
+++ llvm/lib/CodeGen/TargetRegisterInfo.cpp
@@ -234,8 +234,9 @@
   // this physreg.
   const TargetRegisterClass *BestRC = nullptr;
   for (const TargetRegisterClass *RC : regclasses()) {
-    if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) &&
-        (!BestRC || BestRC->hasSubClass(RC)))
+    if ((!Ty.isValid() ||
+         (RC->isAllocatable() && isTypeLegalForClass(*RC, Ty))) &&
+        RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
       BestRC = RC;
   }
 


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