[PATCH] D118222: [RISCV] Split f64 undef into two integer undefs

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead created this revision.
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So that no store instruction will be generated.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118222

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8353,27 +8353,37 @@
   DebugLoc DL = MI.getDebugLoc();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
+  const MachineRegisterInfo &RegInfo = MF.getRegInfo();
   Register LoReg = MI.getOperand(0).getReg();
   Register HiReg = MI.getOperand(1).getReg();
   Register SrcReg = MI.getOperand(2).getReg();
-  const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
-  int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
 
-  TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
-                          RI);
-  MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
-  MachineMemOperand *MMOLo =
-      MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8));
-  MachineMemOperand *MMOHi = MF.getMachineMemOperand(
-      MPI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8));
-  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
-      .addFrameIndex(FI)
-      .addImm(0)
-      .addMemOperand(MMOLo);
-  BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
-      .addFrameIndex(FI)
-      .addImm(4)
-      .addMemOperand(MMOHi);
+  // If the source is undef, we split it into two integer undefs. No need to
+  // remove SrcDef since pass `processimpdefs` will do the favor.
+  MachineInstr* SrcDef = RegInfo.getVRegDef(SrcReg);
+  if (SrcDef->isImplicitDef()) {
+    BuildMI(*BB, MI, DL, TII.get(TargetOpcode::IMPLICIT_DEF), LoReg);
+    BuildMI(*BB, MI, DL, TII.get(TargetOpcode::IMPLICIT_DEF), HiReg);
+  } else {
+    const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
+    int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
+
+    TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI,
+                            SrcRC, RI);
+    MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
+    MachineMemOperand *MMOLo =
+        MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8));
+    MachineMemOperand *MMOHi = MF.getMachineMemOperand(
+        MPI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8));
+    BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
+        .addFrameIndex(FI)
+        .addImm(0)
+        .addMemOperand(MMOLo);
+    BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
+        .addFrameIndex(FI)
+        .addImm(4)
+        .addMemOperand(MMOHi);
+  }
   MI.eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }


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