[PATCH] D118215: [RISCV] Add support for matching vwmulsu from fixed vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7269
 
+  // For VWMULSU.vx vd, vs2, rs1. The signed extern op must be vs2,
+  // so if Op0 IsSignExt it can not be a vector extended from scalar.
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This code doesn't make sense to me. Is it still needed even after removing the `SDNPCommutative` flag?

Once you've identified a VSEXT and VZEXT everything should be fine. Tablegen should only be able to select the splat on zero extend operand.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118215/new/

https://reviews.llvm.org/D118215