[PATCH] D118215: [RISCV] Add support for matching vwmulsu from fixed vectors.

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng marked an inline comment as done.
Chenbing.Zheng added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7272
+  if (IsVWMULSU) {
+    SDValue TmpOp = Op0.getOperand(0).getOperand(1);
+    if (TmpOp.getOpcode() == ISD::BUILD_VECTOR ||
----------------
Chenbing.Zheng wrote:
> craig.topper wrote:
> > i'm not sure what Op0.getOperand(0).getOperand(1) is.
> > 
> > `Op0` is the RISCVISD::VSEXT_VL
> > `Op0.getOperand(0)` is the input to the RISCVISD::VSEXT_VL
> > `Op0.getOperand(0).getOperand(1)` is the input to the input that, but we don't even know the opcode or how many inputs it has.
> > 
> > 
> > But I don't know why we need to check anything special here.
> For this case,  I think we couldn't combine it to  vwmulsu.vx v8, v9, a1, because vwmulsu.vx signed op is only for v9 here. So I check some specil opcode here , which generate during the process of build_vec from scalar.
> 
> define <2 x i16> @vwmulsu_vx_v2i16_swap(<2 x i8>* %x, i8 %y) {
>   %a = load <2 x i8>, <2 x i8>* %x
>   %b = insertelement <2 x i8> undef, i8 %y, i32 0
>   %c = shufflevector <2 x i8> %b, <2 x i8> undef, <2 x i32> zeroinitializer
>   %d = zext <2 x i8> %a to <2 x i16>
>   %e = sext <2 x i8> %c to <2 x i16>  // here sext for %c it is build from %y
>   %f = mul <2 x i16> %d, %e
>   ret <2 x i16> %f
> }
I rewrite here, is it better now?


Repository:
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  https://reviews.llvm.org/D118215/new/

https://reviews.llvm.org/D118215