[PATCH] D118215: [RISCV] Add support for matching vwmulsu from fixed vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7272
+  if (IsVWMULSU) {
+    SDValue TmpOp = Op0.getOperand(0).getOperand(1);
+    if (TmpOp.getOpcode() == ISD::BUILD_VECTOR ||
----------------
i'm not sure what Op0.getOperand(0).getOperand(1) is.

`Op0` is the RISCVISD::VSEXT_VL
`Op0.getOperand(0)` is the input to the RISCVISD::VSEXT_VL
`Op0.getOperand(0).getOperand(1)` is the input to the input that, but we don't even know the opcode or how many inputs it has.


But I don't know why we need to check anything special here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118215/new/

https://reviews.llvm.org/D118215