[PATCH] D118215: [RISCV] Add support for matching vwmulsu from fixed vectors.

[Chenbing.Zheng via Phabricator via llvm-commits]

Chenbing.Zheng created this revision.
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According to  riscv-v-spec-1.0, widening signed(vs2)-unsigned integer multiply
vwmulsu.vv vd, vs2, vs1, vm # vector-vector
vwmulsu.vx vd, vs2, rs1, vm # vector-scalar

It is worth noting that signed op is only for vs2. 
For vwmulsu.vv, we can swap two ops, and don't care which is sign extension,
but for vwmulsu.vx signExt  can not be a vector extended from scalar (rs1).
I specifically added two functions ending with _swap in the test case.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D118215

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-vwmulsu.ll

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