[PATCH] D118160: [RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp:11
+// beqz/bnez instructions. For instance, the copy instruction in the code below
+// can be removed because the beqz jumps to BB#2 when W0 is zero.
+//  BB#1:
----------------
liaolucy wrote:
> W0 is typo?
Copy and pasted from AArch64. I'll fix. Thanks


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Comment at: llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp:95
+
+  MachineBasicBlock::iterator CondBr = PredMBB->getLastNonDebugInstr();
+  if (CondBr == PredMBB->end())
----------------
liaolucy wrote:
> select_cc also generates beq, I'm not sure should handle it?
This pass runs after register allocation so select_cc will already have been expanded into control flow before we here. I think all the test changes started as select_cc.


Repository:
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  https://reviews.llvm.org/D118160/new/

https://reviews.llvm.org/D118160